From WikiChip
Difference between revisions of "intel/xeon e5/e5-4655 v4"
(Add turbo frequencies per-core) |
|||
(13 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon E5-4655 v4}} | {{intel title|Xeon E5-4655 v4}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=Xeon E5-4655 v4 |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=E5-4655 v4 | |
− | | designer | + | |part number=CM8066002065000 |
− | | manufacturer | + | |s-spec=SR2SH |
− | | model number | + | |s-spec qs=QKSX |
− | | part number | + | |market=Server |
− | | | + | |first announced=June 20, 2016 |
− | | | + | |first launched=June 20, 2016 |
− | + | |release price=$4616 | |
− | | market | + | |family=Xeon E5 |
− | | first announced | + | |series=E5-4000 |
− | | first launched | + | |locked=Yes |
− | + | |frequency=2,500 MHz | |
− | + | |turbo frequency1=3,200 MHz | |
− | | release price | + | |turbo frequency2=3,200 MHz |
− | + | |turbo frequency3=3,000 MHz | |
− | | family | + | |turbo frequency4=2,900 MHz |
− | | series | + | |turbo frequency5=2,800 MHz |
− | | locked | + | |turbo frequency6=2,700 MHz |
− | | frequency | + | |turbo frequency7=2,600 MHz |
− | | turbo | + | |turbo frequency8=2,600 MHz |
− | | turbo | + | |turbo frequency=Yes |
− | | turbo | + | |bus type=QPI |
− | | bus type | + | |bus speed=4,800 MHz |
− | | bus speed | + | |bus links=2 |
− | | bus rate | + | |bus rate=9.6 GT/s |
− | + | |clock multiplier=25 | |
− | | clock multiplier | + | |cpuid=406F1 |
− | | | + | |isa=x86-64 |
− | | | + | |isa family=x86 |
− | + | |microarch=Broadwell | |
− | | | + | |platform=Grantley EP 4S |
− | + | |chipset=C610 Series | |
− | | microarch | + | |core name=Broadwell EP |
− | | platform | + | |core family=6 |
− | | chipset | + | |core model=4F |
− | | core name | + | |core stepping=M0 |
− | | core family | + | |process=14 nm |
− | | core model | + | |transistors=3,200,000,000 |
− | | core stepping | + | |technology=CMOS |
− | | process | + | |word size=64 bit |
− | | transistors | + | |core count=8 |
− | | technology | + | |thread count=16 |
− | + | |max memory=1,536 GiB | |
− | | word size | + | |max cpus=4 |
− | | core count | + | |v core=1.82 V |
− | | thread count | + | |v io=1.2 V |
− | + | |v io tolerance=3% | |
− | | max memory | + | |tdp=135 W |
− | + | |tcase min=0 °C | |
− | | | + | |tcase max=82 °C |
− | | v core | + | |tstorage min=-25 °C |
− | + | |tstorage max=125 °C | |
− | | v io | + | |die size=246.24 mm² |
− | | v io tolerance | + | |packaging=Yes |
− | + | |package 0=FCLGA-2011-v3 | |
− | | tdp | + | |package 0 type=FCLGA |
− | + | |package 0 pins=2011 | |
− | + | |package 0 pitch=0.8814 mm | |
− | + | |package 0 width=52.5 mm | |
− | + | |package 0 length=45.0 mm | |
− | + | |package 0 height=5.316 mm | |
− | + | |socket 0=LGA-2011-v3 | |
− | | tcase min | + | |socket 0 type=LGA |
− | | tcase max | ||
− | | tstorage min | ||
− | | tstorage max | ||
− | |||
− | | packaging | ||
− | | package 0 | ||
− | | package 0 type | ||
− | | package 0 pins | ||
− | | package 0 pitch | ||
− | | package 0 width | ||
− | | package 0 length | ||
− | | package 0 height | ||
− | | socket 0 | ||
− | | socket 0 type | ||
}} | }} | ||
The '''Xeon E5-4655 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | The '''Xeon E5-4655 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | ||
Line 96: | Line 82: | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core, write-back) | |l1d extra=(per core, write-back) | ||
− | |l2 cache= | + | |l2 cache=2 MiB |
|l2 break=8x256 KiB | |l2 break=8x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
Line 104: | Line 90: | ||
|l3 desc=20-way set associative | |l3 desc=20-way set associative | ||
|l3 extra=(shared, per core, write-back) | |l3 extra=(shared, per core, write-back) | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This microprocessor has no [[integrated graphics processing unit]]. | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = DDR4-2133 | ||
+ | | controllers = 1 | ||
+ | | channels = 4 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = 63.58 GiB/s | ||
+ | | bandwidth schan = 15.89 GiB/s | ||
+ | | bandwidth dchan = 31.79 GiB/s | ||
+ | | max memory = 1,536 GiB | ||
+ | | pae = 46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 40 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | vpro = | ||
+ | | ht = Yes | ||
+ | | tbt1 = | ||
+ | | tbt2 = Yes | ||
+ | | tbmt3 = | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | ept = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | pclmul = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
+ | | intel at = | ||
+ | | intel ipt = | ||
}} | }} |
Latest revision as of 16:26, 31 January 2024
Edit Values | |
Xeon E5-4655 v4 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-4655 v4 |
Part Number | CM8066002065000 |
S-Spec | SR2SH QKSX (QS) |
Market | Server |
Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
Release Price | $4616 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-4000 |
Locked | Yes |
Frequency | 2,500 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,200 MHz (1 core), 3,200 MHz (2 cores), 3,000 MHz (3 cores), 2,900 MHz (4 cores), 2,800 MHz (5 cores), 2,700 MHz (6 cores), 2,600 MHz (7 cores), 2,600 MHz (8 cores) |
Bus type | QPI |
Bus speed | 4,800 MHz |
Bus rate | 2 × 9.6 GT/s |
Clock multiplier | 25 |
CPUID | 406F1 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grantley EP 4S |
Chipset | C610 Series |
Core Name | Broadwell EP |
Core Family | 6 |
Core Model | 4F |
Core Stepping | M0 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 135 W |
Tcase | 0 °C – 82 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-4655 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
8x256 KiB 8-way set associative (per core, write-back) |
L3$ | 30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB |
8x3.75 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 63.58 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
Expansion Options
|
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||
|
Facts about "Xeon E5-4655 v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-4655 v4 - Intel#io + |
base frequency | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
bus links | 2 + |
bus rate | 9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) + |
bus speed | 4,800 MHz (4.8 GHz, 4,800,000 kHz) + |
bus type | QPI + |
chipset | C610 Series + |
clock multiplier | 25 + |
core count | 8 + |
core family | 6 + |
core model | 4F + |
core name | Broadwell EP + |
core stepping | M0 + |
core voltage | 1.82 V (18.2 dV, 182 cV, 1,820 mV) + |
cpuid | 406F1 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon E5 + |
first announced | June 20, 2016 + |
first launched | June 20, 2016 + |
full page name | intel/xeon e5/e5-4655 v4 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
io voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
io voltage tolerance | 3% + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |
ldate | June 20, 2016 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 355.15 K (82 °C, 179.6 °F, 639.27 °R) + |
max cpu count | 4 + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max pcie lanes | 40 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Broadwell + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E5-4655 v4 + |
name | Xeon E5-4655 v4 + |
part number | CM8066002065000 + |
platform | Grantley EP 4S + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 4,616.00 (€ 4,154.40, £ 3,738.96, ¥ 476,971.28) + |
s-spec | SR2SH + |
s-spec (qs) | QKSX + |
series | E5-4000 + |
smp max ways | 4 + |
tdp | 135 W (135,000 mW, 0.181 hp, 0.135 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 3,200,000,000 + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
turbo frequency (2 cores) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
turbo frequency (3 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (4 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (5 cores) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
turbo frequency (6 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (7 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (8 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |