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Difference between revisions of "intel/xeon e5/e5-2650 v4"
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(Created page with "{{intel title|Xeon E5-2650 v4}} {{mpu | name = Xeon E5-2650 v4 | no image = Yes | image = | image size = | caption...")
 
(add the all core turbo frequency)
 
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{{intel title|Xeon E5-2650 v4}}
 
{{intel title|Xeon E5-2650 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2650 v4
 
| name                = Xeon E5-2650 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2650 v4
 
| model number        = E5-2650 v4
 
| part number        = CM8066002031103
 
| part number        = CM8066002031103
−
| part number 1       = BX80660E52650V4
+
| part number 2       = BX80660E52650V4
−
| part number 2      =
 
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 2,900 MHz
 
| turbo frequency1    = 2,900 MHz
−
| turbo frequency2    =  
+
| turbo frequency2    =
 +
| turbo frequency3    =
 +
| turbo frequency4    =
 +
| turbo frequency5    =
 +
| turbo frequency6    =
 +
| turbo frequency7    =
 +
| turbo frequency8    =
 +
| turbo frequency9    =
 +
| turbo frequency10  = 2,500 MHz
 +
| turbo frequency11  = 2,500 MHz
 +
| turbo frequency12  = 2,500 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,800 MHz
 
| bus speed          = 4,800 MHz
Line 34: Line 44:
 
| s-spec              = SR2N3
 
| s-spec              = SR2N3
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QK8Y
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            = Grantley EP 2S
 
| platform            = Grantley EP 2S
Line 42: Line 54:
 
| core name          = Broadwell EP
 
| core name          = Broadwell EP
 
| core family        = 6
 
| core family        = 6
−
| core model          = 15
+
| core model          = 4F
 
| core stepping      = M0
 
| core stepping      = M0
 
| process            = 14 nm
 
| process            = 14 nm
Line 54: Line 66:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 84: Line 96:
 
}}
 
}}
 
The '''Xeon E5-2650 v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 2.9 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-2650 v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 2.9 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=3 MiB
 +
|l2 break=12x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=30 MiB
 +
|l3 break=12x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2400
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 71.53 GiB/s
 +
| bandwidth schan    = 17.88 GiB/s
 +
| bandwidth dchan    = 35.76 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 +
}}
 +
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171002-00075.html|test_timestamp=2017-10-03 11:47:03-0400|chip_count=2|core_count=24|copies_count=48|vendor=Inspur Corporation|system=Inspur NF5170M4 (Intel Xeon E5-2650 v4)|SPECrate2017_int_base=105|SPECrate2017_int_peak=112}}
 +
}}

Latest revision as of 22:36, 26 March 2023

Edit Values
Xeon E5-2650 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2650 v4
Part NumberCM8066002031103,
BX80660E52650V4
S-SpecSR2N3
QK8Y (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$1166.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency2,900 MHz (1 core),
2,500 MHz (10 cores),
2,500 MHz (11 cores),
2,500 MHz (12 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores12
Threads24
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP105 W
Tcase0 °C – 80 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2650 v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 2.9 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 384 KiB
393,216 B
0.375 MiB
12x32 KiB 8-way set associative (per core, write-back)
L1D$ 384 KiB
393,216 B
0.375 MiB
12x32 KiB 8-way set associative (per core, write-back)
L2$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
12x256 KiB 8-way set associative (per core, write-back)
L3$ 30 MiB
30,720 KiB
31,457,280 B
0.0293 GiB
12x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-10-03 11:47:03-0400
Chips: 2, Cores: 24, Copies: 48
benchmarks.svg
Vendor: Inspur Corporation
System: Inspur NF5170M4 (Intel Xeon E5-2650 v4)
SPECrate2017_int_base: 105
SPECrate2017_int_peak: 112
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2650_v4&oldid=101535"
Facts about "Xeon E5-2650 v4 - Intel"
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Xeon E5-2650 v4 - Intel#io + and Xeon E5-2650 v4 - Intel +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier22 +
core count12 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingM0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area306.18 mm² (0.475 in², 3.062 cm², 306,180,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-2650 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
isax86-64 +
isa familyx86 +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ description20-way set associative +
l3$ size30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature353.15 K (80 °C, 176 °F, 635.67 °R) +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2650 v4 +
nameXeon E5-2650 v4 +
part numberCM8066002031103 + and BX80660E52650V4 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,166.00 (€ 1,049.40, £ 944.46, ¥ 120,482.78) +
s-specSR2N3 +
s-spec (qs)QK8Y +
seriesE5-2000 +
smp max ways2 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count24 +
transistor count4,700,000,000 +
turbo frequency (10 cores)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (11 cores)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (12 cores)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (1 core)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +