Difference between revisions of "amd/epyc/7551p"

	Edit Values
	EPYC 7551P
	General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	7551P
Part Number	PS755PBDVIHAF
Market	Server
Introduction	June 20, 2017 (announced); June 20, 2017 (launched)
Release Price	$2,100
Shop	Amazon
	General Specs
Family	EPYC
Series	7000
Locked	No
Frequency	2,000 MHz
Turbo Frequency	3,000 MHz (1 core),; 3,000 MHz (2 cores),; 3,000 MHz (3 cores),; 3,000 MHz (4 cores),; 3,000 MHz (5 cores),; 3,000 MHz (6 cores),; 3,000 MHz (7 cores),; 3,000 MHz (8 cores),; 3,000 MHz (9 cores),; 3,000 MHz (10 cores),; 3,000 MHz (11 cores),; 3,000 MHz (12 cores),; 2,550 MHz (13 cores),; 2,550 MHz (14 cores),; 2,550 MHz (15 cores),; 2,550 MHz (16 cores),; 2,550 MHz (17 cores),; 2,550 MHz (18 cores),; 2,550 MHz (19 cores),; 2,550 MHz (20 cores),; 2,550 MHz (21 cores),; 2,550 MHz (22 cores),; 2,550 MHz (23 cores),; 2,550 MHz (24 cores),; 2,550 MHz (25 cores),; 2,550 MHz (26 cores),; 2,550 MHz (27 cores),; 2,550 MHz (28 cores),; 2,550 MHz (29 cores),; 2,550 MHz (30 cores),; 2,550 MHz (31 cores),; 2,550 MHz (32 cores)
Clock multiplier	20
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen
Core Name	Naples
Core Family	23
Core Model	1
Core Stepping	B2
Process	14 nm
Transistors	19,200,000,000
Technology	CMOS
Die	213 mm²
MCP	Yes (4 dies)
Word Size	64 bit
Cores	32
Threads	64
Max Memory	2 TiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	180 W
Tcase	0 °C – 81 °C
	Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

Latest revision as of 11:30, 18 March 2023

EPYC 7551P is a 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

3 MiB

3,072 KiB
3,145,728 B

L1I$	2 MiB 2,048 KiB 2,097,152 B	32x64 KiB	4-way set associative
L1D$	1 MiB 1,024 KiB 1,048,576 B	32x32 KiB	8-way set associative	write-back

L2$

16 MiB

16,384 KiB
16,777,216 B
0.0156 GiB

		32x512 KiB	8-way set associative	write-back

L3$

64 MiB

65,536 KiB
67,108,864 B
0.0625 GiB

		8x8 MiB	16-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	2 TiB
Controllers	8
Channels	8
Max Bandwidth	158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s
Bandwidth	Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s Octa 158.95 GiB/s

Expansions[edit]

The EPYC 7551P has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	128
Configs	8x16, 32x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
SSE4a	Streaming SIMD Extensions 4a
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
SMT	Simultaneous Multithreading
AMD-Vi	AMD-Vi (I/O MMU virtualization)
AMD-V	AMD Virtualization
SME	Secure Memory Encryption
TSME	Transparent SME
SEV	Secure Encrypted Virtualization
SenseMI	SenseMI Technology

@@ Line 1: / Line 1: @@
 {{amd title|EPYC 7551P}}
-{{mpu
+{{chip
 |name=EPYC 7551P
 |no image=Yes
 |designer=AMD
 |manufacturer=GlobalFoundries
-|model number=7351P
+|model number=7551P
+|part number=PS755PBDVIHAF
 |market=Server
 |first announced=June 20, 2017
+|first launched=June 20, 2017
+|release price=$2,100
 |family=EPYC
 |series=7000
@@ Line 13: / Line 16: @@
 |frequency=2,000 MHz
 |turbo frequency1=3,000 MHz
-|bus links=4
+|turbo frequency2=3,000 MHz
-|bus rate=8 GT/s
+|turbo frequency3=3,000 MHz
+|turbo frequency4=3,000 MHz
+|turbo frequency5=3,000 MHz
+|turbo frequency6=3,000 MHz
+|turbo frequency7=3,000 MHz
+|turbo frequency8=3,000 MHz
+|turbo frequency9=3,000 MHz
+|turbo frequency10=3,000 MHz
+|turbo frequency11=3,000 MHz
+|turbo frequency12=3,000 MHz
+|turbo frequency13=2,550 MHz
+|turbo frequency14=2,550 MHz
+|turbo frequency15=2,550 MHz
+|turbo frequency16=2,550 MHz
+|turbo frequency17=2,550 MHz
+|turbo frequency18=2,550 MHz
+|turbo frequency19=2,550 MHz
+|turbo frequency20=2,550 MHz
+|turbo frequency21=2,550 MHz
+|turbo frequency22=2,550 MHz
+|turbo frequency23=2,550 MHz
+|turbo frequency24=2,550 MHz
+|turbo frequency25=2,550 MHz
+|turbo frequency26=2,550 MHz
+|turbo frequency27=2,550 MHz
+|turbo frequency28=2,550 MHz
+|turbo frequency29=2,550 MHz
+|turbo frequency30=2,550 MHz
+|turbo frequency31=2,550 MHz
+|turbo frequency32=2,550 MHz
 |clock multiplier=20
 |isa=x86-64
@@ Line 20: / Line 52: @@
 |microarch=Zen
 |core name=Naples
+|core family=23
+|core model=1
+|core stepping=B2
 |process=14 nm
 |transistors=19,200,000,000
 |technology=CMOS
-|die area=195.228 mm²
+|die area=213 mm²
-|die length=8.87 mm
-|die width=22.01 mm
 |mcp=Yes
 |die count=4
@@ Line 33: / Line 66: @@
 |max cpus=1
 |max memory=2 TiB
-|package module 1={{packages/amd/socket sp3}}
+|tdp=180 W
+|tcase min=0 °C
+|tcase max=81 °C
+|package name 1=amd,socket_sp3
 }}
-'''EPYC 7551P''' is a {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.
+'''EPYC 7551P''' is a {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.
@@ Line 43: / Line 79: @@
 {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 {{cache size
-|l1 cache=1.5 MiB
+|l1 cache=3 MiB
-|l1i cache=1 MiB
+|l1i cache=2 MiB
-|l1i break=16x64 KiB
+|l1i break=32x64 KiB
 |l1i desc=4-way set associative
-|l1d cache=512 KiB
+|l1d cache=1 MiB
-|l1d break=16x32 KiB
+|l1d break=32x32 KiB
 |l1d desc=8-way set associative
 |l1d policy=write-back
-|l2 cache=8 MiB
+|l2 cache=16 MiB
-|l2 break=16x512 KiB
+|l2 break=32x512 KiB
 |l2 desc=8-way set associative
 |l2 policy=write-back
@@ Line 66: / Line 102: @@
 |ecc=Yes
 |max mem=2 TiB
-|controllers=1
+|controllers=8
 |channels=8
 |max bandwidth=158.95 GiB/s
@@ Line 72: / Line 108: @@
 |bandwidth dchan=39.72 GiB/s
 |bandwidth qchan=79.47 GiB/s
+|bandwidth ochan=158.95 GiB/s
 |bandwidth hchan=119.21 GiB/s
-|bandwidth ochan=158.95 GiB/s
+}}
+== Expansions ==
+The EPYC 7551P has 128 Gen 3 PCIe lanes.
+{{expansions
+| pcie revision      = 3.0
+| pcie lanes         = 128
+| pcie config        = 8x16
+| pcie config 2      = 32x4
+| sata revision      =
+| sata ports         =
+| usb revision       =
+| usb revision 2     =
+| usb ports          =
+| usb rate           =
+| uart               =
+| uart ports         =
+| gp io              =
 }}
@@ Line 97: / Line 151: @@
 |avx=Yes
 |avx2=Yes
-|avx512=No
 |abm=Yes
 |tbm=No
@@ Line 142: / Line 196: @@
 |amdvi=Yes
 |amdv=Yes
+|amdsme=Yes
+|amdtsme=Yes
+|amdsev=Yes
 |rvi=No
 |smt=Yes

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7551P - AMD#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
clock multiplier	20 +
core count	32 +
core family	23 +
core model	1 +
core name	Naples +
core stepping	B2 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	4 +
family	EPYC +
first announced	June 20, 2017 +
first launched	June 20, 2017 +
full page name	amd/epyc/7551p +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	false +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	4-way set associative +
l1i$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l2$ description	8-way set associative +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description	16-way set associative +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	June 20, 2017 +
manufacturer	GlobalFoundries +
market segment	Server +
max case temperature	354.15 K (81 °C, 177.8 °F, 637.47 °R) +
max cpu count	1 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels	8 +
max pcie lanes	128 +
microarchitecture	Zen +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	7551P +
name	EPYC 7551P +
package	SP3 + and FCLGA-4094 +
part number	PS755PBDVIHAF +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 2,100.00 (€ 1,890.00, £ 1,701.00, ¥ 216,993.00) +
series	7000 +
smp max ways	1 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-2666 +
tdp	180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technology	CMOS +
thread count	64 +
transistor count	19,200,000,000 +
turbo frequency (10 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (11 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (12 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (13 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (14 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (15 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (16 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (17 cores)	2,550 MHz +
turbo frequency (18 cores)	2,550 MHz +
turbo frequency (19 cores)	2,550 MHz +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (20 cores)	2,550 MHz +
turbo frequency (21 cores)	2,550 MHz +
turbo frequency (22 cores)	2,550 MHz +
turbo frequency (23 cores)	2,550 MHz +
turbo frequency (24 cores)	2,550 MHz +
turbo frequency (25 cores)	2,550 MHz +
turbo frequency (26 cores)	2,550 MHz +
turbo frequency (27 cores)	2,550 MHz +
turbo frequency (28 cores)	2,550 MHz +
turbo frequency (29 cores)	2,550 MHz +
turbo frequency (2 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (30 cores)	2,550 MHz +
turbo frequency (31 cores)	2,550 MHz +
turbo frequency (32 cores)	2,550 MHz +
turbo frequency (3 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (4 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (5 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (6 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (7 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (8 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (9 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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