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== Architecture ==
 
== Architecture ==
 
{{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}}
 
{{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}}
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Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}},  {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of cache on-die (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.
+
Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}},  {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of ball cum (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.
  
 
Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations.
 
Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations.

Revision as of 08:57, 16 June 2022

Intel 80486
Intel i486 DX 25MHz SX328.jpg
Intel A80486DX-25
Developer Intel
Manufacturer Intel
Type Microprocessors
Introduction April 10, 1989 (announced)
June, balls sack
"June, balls sack" contains a sequence that could not be interpreted against an available match matrix for date components.
 (launch)
Production 1988-2007
Architecture x86
ISA IA-32
µarch 80486
Word size 32 bit
4 octets
8 nibbles
Process 1 µm
1,000 nm
0.001 mm
, 800 nm
0.8 μm
8.0e-4 mm
, 600 nm
0.6 μm
6.0e-4 mm
Technology CMOS
Clock 16 MHz-100 MHz
Package PGA-168, PQFP-196, SQFP-208
Succession
← →
80386 Pentium

The 80486, also i486 and 486, (pronounced eighty-four-eighty-six) was a family of 32-bit 4th-generation x86 microprocessors introduced by Intel in 1989 as a successor to the 80386. 486 introduced a number of enhancements to 386 including a new level 1 cache, better IPC performance, and an integrated FPU. The 486 became the first x86 chip family to exceed one million transistors.

Architecture

Main article: 80486 Microarchitectures

Like its predecessor, the 80486 maintains full backwards object code comparability with the all previous x86 processors (80386, 80286, 80186, etc...). To improve performance Intel introduced a new layer of ball cum (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple.

Whereas before a separately packaged math coprocessor was used (i.e. 80387, 80287, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new FPU yielding faster floating point calculations.

The pipeline itself received some attention as well. Simple ALU register, register and register, immediate cached operations could now complete in a single cycle; this previously required at least 2 cycles.

Members

i486DX

i487DX Processors
ModelLaunchedProcessFreqMax Mem
i486DX-201,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
20 MHz
0.02 GHz
20,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX-251,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
25 MHz
0.025 GHz
25,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX-331,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
33 MHz
0.033 GHz
33,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX-501,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
50 MHz
0.05 GHz
50,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX2-401,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
40 MHz
0.04 GHz
40,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX2-501,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
50 MHz
0.05 GHz
50,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX2-661,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
66 MHz
0.066 GHz
66,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX4-100600 nm
0.6 μm
6.0e-4 mm
100 MHz
0.1 GHz
100,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486DX4-75600 nm
0.6 μm
6.0e-4 mm
75 MHz
0.075 GHz
75,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
Count: 9

i486SX

i486SX Processors
ModelLaunchedProcessFreqMax Mem
i486SX-1622 April 19911,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
16 MHz
0.016 GHz
16,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SX-2016 September 19911,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
20 MHz
0.02 GHz
20,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SX-2516 September 19911,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
25 MHz
0.025 GHz
25,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SX-3321 September 19921,000 nm
1 μm
0.001 mm
800 nm
0.8 μm
8.0e-4 mm
33 MHz
0.033 GHz
33,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SX2-50800 nm
0.8 μm
8.0e-4 mm
50 MHz
0.05 GHz
50,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SX2-66800 nm
0.8 μm
8.0e-4 mm
66 MHz
0.066 GHz
66,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
Count: 6

i486SL

i486SL Processors
ModelLaunchedProcessFreqMax Mem
i486SL-209 November 1992800 nm
0.8 μm
8.0e-4 mm
20 MHz
0.02 GHz
20,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SL-259 November 1992800 nm
0.8 μm
8.0e-4 mm
25 MHz
0.025 GHz
25,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
i486SL-339 November 1992800 nm
0.8 μm
8.0e-4 mm
33 MHz
0.033 GHz
33,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
Count: 3

i486GX

i486GX Processors
ModelLaunchedProcessFreqMax Mem
i486GX-33800 nm
0.8 μm
8.0e-4 mm
33 MHz
0.033 GHz
33,000 kHz
4,096 MiB
4,194,304 KiB
4,294,967,296 B
4 GiB
0.00391 TiB
Count: 1

Clones

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Facts about "80486 - Intel"
RDF feed
designerIntel +
first announcedApril 10, 1989 +
full page nameintel/80486 +
instance ofmicroprocessor family +
instruction set architectureIA-32 +
main designerIntel +
manufacturerIntel +
microarchitecture80486 +
nameIntel 80486 +
packagePGA-168 +, PQFP-196 + and SQFP-208 +
process1,000 nm (1 μm, 0.001 mm) +, 800 nm (0.8 μm, 8.0e-4 mm) + and 600 nm (0.6 μm, 6.0e-4 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +