From WikiChip
File list
This special page shows all uploaded files.
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Date | Name | Thumbnail | Size | User | Description | Versions |
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14:30, 20 October 2019 | wikichip-main-box-z15.jpg (file) | ![]() |
681 KB | David | IBM {{ibm|z15|l=arch}} box. | 1 |
01:33, 19 October 2019 | archer sc.jpg (file) | ![]() |
1.14 MB | David | {{sc|ARCHER}} supercomputer. Photo by EPCC. | 1 |
01:23, 19 October 2019 | archer logo.png (file) | ![]() |
36 KB | David | {{sc|ARCHER}} logo | 1 |
10:58, 16 October 2019 | fsd comp 6.jpg (file) | ![]() |
848 KB | David | Tesla {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
10:58, 16 October 2019 | fsd comp 5.jpg (file) | ![]() |
852 KB | David | Tesla {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
10:58, 16 October 2019 | fsd comp 4.jpg (file) | ![]() |
855 KB | David | Tesla {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
10:58, 16 October 2019 | fsd comp 3.jpg (file) | ![]() |
869 KB | David | Tesla {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
10:58, 16 October 2019 | fsd comp 2.jpg (file) | ![]() |
878 KB | David | Tesla (car company) {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
10:57, 16 October 2019 | fsd comp 1.jpg (file) | ![]() |
879 KB | David | Tesla (car company) {{teslacar|FSD Chip}} computer board. Image by WikiChip. | 1 |
01:00, 16 October 2019 | sph dl compute grid.svg (file) | ![]() |
77 KB | David | 3 | |
00:57, 16 October 2019 | spring hill overview.svg (file) | ![]() |
42 KB | David | 3 | |
22:42, 15 October 2019 | sph batch 4x6.svg (file) | ![]() |
38 KB | David | Intel {{intel|Spring Hill|l=arch}} with six applications with batch size of 4. Diagram by WikiChip. | 1 |
22:42, 15 October 2019 | sph batch 1x2.svg (file) | ![]() |
27 KB | David | Intel {{intel|Spring Hill|l=arch}} with two applications with batch size of 1. Diagram by WikiChip. | 1 |
22:12, 15 October 2019 | sph soc.svg (file) | ![]() |
65 KB | David | 2 | |
22:05, 15 October 2019 | sph ice.svg (file) | ![]() |
103 KB | David | Intel {{intel|Spring Hill|l=arch}} ICE. Diagram by WikiChip. | 1 |
19:11, 15 October 2019 | sph board.jpg (file) | ![]() |
46 KB | David | Intel {{intel|Spring Hill|l=arch}} board. | 1 |
19:10, 15 October 2019 | spring hill board.JPG (file) | 867 KB | David | Intel {{intel|Spring Hill|l=arch}} board. | 1 | |
14:20, 15 October 2019 | exynos 7904 (back).png (file) | ![]() |
209 KB | David | Samsung Exynos 7904, back image. | 1 |
14:19, 15 October 2019 | exynos 7904 (front).png (file) | ![]() |
33 KB | David | Samsung Exynos 7904, front image. | 1 |
00:50, 14 October 2019 | 5nm densities.svg (file) | ![]() |
84 KB | David | 5 | |
22:27, 13 October 2019 | ss-5nm-cells.svg (file) | ![]() |
59 KB | David | corrected CPP on HD cell | 2 |
05:06, 13 October 2019 | kunpeng roadmap (2019).jpeg (file) | ![]() |
201 KB | David | Huawei {{huawei|Kunpeng}} roadmap, 2019. | 1 |
08:23, 7 October 2019 | cascade-lake-w (front).png (file) | ![]() |
1.45 MB | David | Intel {{intel|Cascade Lake W|l=core}} | 1 |
15:01, 3 October 2019 | intel-ref-248966-042b.pdf (file) | ![]() |
9.15 MB | David | Intel IA-32 Architecture Optimization Reference Manual 248966, Revision 42b. See {{intel|Documents}}. | 1 |
00:19, 26 September 2019 | hanguang800.jpg (file) | ![]() |
628 KB | David | Hanguang 800. Image by Alibaba. | 1 |
21:06, 14 September 2019 | z15 block diagram.svg (file) | ![]() |
136 KB | David | IBM {{ibm|z15|l=arch}} block diagram by WikiChip. | 1 |
21:03, 14 September 2019 | z15 chip block diagram.svg (file) | ![]() |
74 KB | David | 2 | |
19:47, 14 September 2019 | z15 sc floorplan.png (file) | ![]() |
589 KB | David | IBM {{ibm|z15|z15 system controller}} floorplan. Image by IBM. | 1 |
19:47, 14 September 2019 | z15 cp floorplan.png (file) | ![]() |
798 KB | David | IBM {{ibm|z15|z15 central processor}} floorplan. Image by IBM. | 1 |
19:47, 14 September 2019 | z15 core floorplan.png (file) | ![]() |
174 KB | David | IBM {{ibm|z15|z15 core}} floorplan. Image by IBM. | 1 |
12:55, 30 August 2019 | cerebras logo.svg (file) | ![]() |
13 KB | David | Cerebras logo | 1 |
00:11, 24 August 2019 | msfp11 encoding format.svg (file) | ![]() |
14 KB | David | 2 | |
23:58, 23 August 2019 | msfp8 encoding format.svg (file) | ![]() |
11 KB | David | msfp8 | 1 |
18:39, 10 August 2019 | ice lake io subsystem.svg (file) | ![]() |
55 KB | David | Intel {{intel|Ice Lake|l=arch}} I/O subsystem. Diagram by WikiChip. | 1 |
15:14, 10 August 2019 | intel type-c ice lake 4p.svg (file) | ![]() |
40 KB | David | Type-C configuration in Intel {{intel|Ice Lake|l=arch}} with four ports. Diagram by WikiChip. | 1 |
15:08, 10 August 2019 | intel type-c ice lake.svg (file) | ![]() |
27 KB | David | Type-C configuration in Intel {{intel|Ice Lake|l=arch}}. Diagram by WikiChip. | 1 |
14:44, 10 August 2019 | intel type-c old.svg (file) | ![]() |
30 KB | David | Type-C configuration prior to Intel {{intel|Ice Lake|l=arch}}. Diagram by WikiChip. | 1 |
22:08, 7 August 2019 | wikichip-main-box-rome.jpg (file) | ![]() |
14 KB | David | 1 | |
21:05, 6 August 2019 | wikichip-main-box-cfl.jpg (file) | ![]() |
191 KB | David | 1 | |
13:24, 6 August 2019 | epyc naming scheme.svg (file) | ![]() |
13 KB | David | {{amd|EPYC}} naming scheme diagram by WikiChip | 1 |
07:06, 5 August 2019 | xeon w naming scheme.svg (file) | ![]() |
10 KB | David | Intel {{intel|Xeon W}} naming scheme. Diagram by WikiChip. | 1 |
00:41, 5 August 2019 | cascade-lake-optane-dimm-encryption.png (file) | ![]() |
531 KB | David | 1 | |
00:24, 5 August 2019 | xeon sp naming change.svg (file) | ![]() |
15 KB | David | 1 | |
00:07, 5 August 2019 | cascade-presistence.png (file) | ![]() |
211 KB | David | Intel {{intel|Cascade Lake|l=arch}} presistence. | 1 |
23:31, 4 August 2019 | cascade lake ap board.JPG (file) | 878 KB | David | Intel {{intel|Cascade Lake|l=arch}} {{intel|Cascade Lake AP|AP|l=arch}} board. | 1 | |
23:30, 4 August 2019 | intel cascade lake ap chip with heatsink.JPG (file) | 913 KB | David | Intel {{intel|Cascade Lake|l=arch}} {{intel|Cascade Lake AP|l=core|AP}} with heatsink. | 1 | |
23:29, 4 August 2019 | cascade lake chip.JPG (file) | 887 KB | David | Intel {{intel|Cascade Lake|l=arch}} chip. | 1 | |
22:35, 4 August 2019 | wikichip-main-box-clx.jpg (file) | ![]() |
301 KB | David | 1 | |
22:07, 4 August 2019 | puma-arch-challenges.png (file) | ![]() |
474 KB | David | {{intel|PUMA}} challenges. | 1 |
22:06, 4 August 2019 | puma-arch-high-level-overview.png (file) | ![]() |
654 KB | David | {{intel|PUMA}} high level overview. | 1 |
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