Semiconductor & Computer Engineering
From WikiChip
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This special page shows all uploaded files.
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| Date | Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 11:39, 1 February 2020 | ai hw summit supermicro ref pod rack.jpeg (file) |  |
2.09 MB | David | Nervana {{nervana|NNP}}-T ref pod rack. | 1 |
| 12:05, 1 February 2020 | knights crest announcement.png (file) |  |
234 KB | David | Nervana {{nervana|Knights Crest|l=arch}} announcement. | 1 |
| 18:43, 1 February 2020 | S9200WK-Reference-Design-Guide.pdf (file) |  |
2.6 MB | David | Intel {{intel|Cascade Lake AP|l=arch}} S9200WK. | 1 |
| 23:33, 1 February 2020 | sd 460 (front).png (file) | .png) |
75 KB | David | Snapdragon 460, front. | 1 |
| 23:34, 1 February 2020 | sd 662 (front).png (file) | .png) |
91 KB | David | Snapdragon 662, front. | 1 |
| 23:39, 1 February 2020 | sd 720g (front).png (file) | .png) |
72 KB | David | Snapdragon 720G, front. | 1 |
| 00:19, 2 February 2020 | sdm720g-brief.pdf (file) |  |
375 KB | David | Sanpdragon 720G PB. | 1 |
| 00:53, 2 February 2020 | sdm662-brief.pdf (file) |  |
325 KB | David | Snapdragon 662 PB. | 1 |
| 01:15, 2 February 2020 | sdm460-brief.pdf (file) |  |
325 KB | David | Snapdragon 460 PB. | 1 |
| 16:03, 4 February 2020 | mlp overview.svg (file) |  |
15 KB | David | Arm {{armh|MLP|l=arch} over diagram by WikiChip. | 1 |
| 14:04, 5 February 2020 | mlp compute engine overview.svg (file) |  |
184 KB | David | {{armh|MLP|l=arch}} Compute Engine overview by WikiChip. | 1 |
| 15:51, 5 February 2020 | mlp ple overview.svg (file) |  |
19 KB | David | 2 | |
| 15:55, 5 February 2020 | mlp block diagram.svg (file) |  |
31 KB | David | Arm {{armh|MLP|l=arch}} block diagram by WikiChip. | 1 |
| 15:58, 5 February 2020 | mlp compute engine block diagram.svg (file) |  |
32 KB | David | arrow correction | 2 |
| 23:07, 7 February 2020 | cray rosetta die plot.jpg (file) |  |
1.88 MB | David | Cray {{cray|Rosetta|l=arch}} die plot. | 1 |
| 15:39, 8 February 2020 | cray slingshot switch.png (file) |  |
1.64 MB | David | Cray {{cray|Slingshot|l=wire}} | 1 |
| 19:47, 8 February 2020 | rosetta crossbars.png (file) |  |
44 KB | David | Cray {{cray|Rosetta|l=arch}} crossbars. | 1 |
| 22:37, 9 February 2020 | OPGA-939.svg (file) |  |
1 KB | QuietRub | Own work based on "AMD Functional Data Sheet, 939-Pin Package", AMD Publ. #31411, Rev. 3.03, May 2005 | 1 |
| 22:38, 9 February 2020 | OPGA-939 lidded D1 diag.svg (file) |  |
35 KB | QuietRub | Own work based on "AMD Functional Data Sheet, 939-Pin Package", AMD Publ. #31411, Rev. 3.03, May 2005 | 1 |
| 22:39, 9 February 2020 | OPGA-939 pinmap.svg (file) |  |
188 KB | QuietRub | Own work based on "AMD Functional Data Sheet, 939-Pin Package", AMD Publ. #31411, Rev. 3.03, May 2005 | 1 |
| 22:32, 10 February 2020 | arm ethos.svg (file) |  |
9 KB | David | Arm {{arm|Ethos}} | 1 |
| 23:18, 10 February 2020 | ethos-n37,57,77 ce config.png (file) |  |
151 KB | David | Arm {{armh|Ethos}} N37,57,77 CE configurations. | 1 |
| 23:26, 11 February 2020 | etacompute-logo.png (file) |  |
47 KB | David | Eta Compute logo. | 1 |
| 01:24, 12 February 2020 | ecm3532 block.png (file) |  |
287 KB | David | Eta Compute {{eta compute|ECM3532}} | 1 |
| 06:50, 15 February 2020 | wikichip-main-box-cha.jpg (file) |  |
73 KB | David | 1 | |
| 18:22, 16 February 2020 | cortex-m55 pipeline.svg (file) |  |
18 KB | David | Arm {{armh|Cortex-M55|l=arch}} pipeline by WikiChip. | 1 |
| 18:39, 16 February 2020 | cortex-m55 general block.png (file) |  |
102 KB | David | Arm {{armh|Cortex-M55|l=arch}} block by Arm. | 1 |
| 19:44, 16 February 2020 | cortex-m55 tcm xbar.svg (file) |  |
30 KB | David | Arm {{armh|Cortex-M55|l=arch}} TCM xbar diagram by WikiChip. | 1 |
| 22:50, 16 February 2020 | helium vector reg file alias.svg (file) |  |
37 KB | David | Arm {{arm|Helium}} vector register file. | 1 |
| 18:46, 21 February 2020 | cha ncore.svg (file) |  |
15 KB | David | 4 | |
| 19:45, 21 February 2020 | cha soc ncore die (logic).png (file) | .png) |
1.96 MB | David | Centaur Technology {{centtech|CHA|CHA NCORE|l=arch}} die logic portion. Photo by Centaur. | 1 |
| 21:59, 21 February 2020 | ncore block diagram.svg (file) |  |
40 KB | David | 4 | |
| 18:24, 22 February 2020 | OPGA-940 AM2 diag.svg (file) |  |
31 KB | QuietRub | Own work based on "Socket AM2 Design Specification", AMD Publ. #31875, Rev. 3.00, May 2008 | 1 |
| 18:26, 22 February 2020 | Socket AM2 diag.svg (file) |  |
16 KB | QuietRub | Own work based on "Socket AM2 Design Specification", AMD Publ. #31875, Rev. 3.00, May 2008 | 1 |
| 18:29, 22 February 2020 | Socket AM2 pinmap.svg (file) |  |
188 KB | QuietRub | Own work. | 1 |
| 18:57, 22 February 2020 | Socket AM2+ pinmap.svg (file) |  |
189 KB | QuietRub | Own work. | 1 |
| 20:42, 28 February 2020 | cea-leti logo.jpg (file) |  |
34 KB | David | CEA-Leti logo. | 1 |
| 03:21, 29 February 2020 | tsarlet compute chiplet.png (file) |  |
917 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} chiplet die. | 1 |
| 03:41, 29 February 2020 | tsarlet compute chiplet (annotated).png (file) | .png) |
802 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} chiplet die, annotated by WikiChip. | 1 |
| 04:19, 29 February 2020 | tsarlet compute chiplet 2.png (file) |  |
1.11 MB | David | CEA Leti {{cealeti|TSARLET|l=arch}} compute chiplet. | 1 |
| 04:19, 29 February 2020 | tsarlet base interposer.png (file) |  |
2.02 MB | David | CEA Leti {{cealeti|TSARLET|l=arch}} base interposer die. | 1 |
| 04:19, 29 February 2020 | tsarlet package.png (file) |  |
624 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} package. | 1 |
| 04:32, 29 February 2020 | tsarlet packaging photo.jpg (file) |  |
135 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} packaging photo. | 1 |
| 16:05, 29 February 2020 | tsarlet overview.png (file) |  |
1.25 MB | David | CEA Leti {{cealeti|tsarlet|l=arch}} overview. | 1 |
| 13:16, 1 March 2020 | tsarlet interposer routing.png (file) |  |
641 KB | David | CEA-Leti {{cealeti|TSARLET|l=arch}} interposer routing. | 1 |
| 19:07, 1 March 2020 | tsarlet interposer with chiplet.png (file) |  |
70 KB | David | CEA-Leti {{cealeti|TSARLET|l=arch}} packaging. | 1 |
| 19:17, 1 March 2020 | tsarlet xsection.png (file) |  |
971 KB | David | CEA-Leti {{cealeti|TSARLET|l=arch}} packaging. | 1 |
| 20:09, 1 March 2020 | tsarlet scvr unit cell circuit.png (file) |  |
43 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} SCVR unit cell circuit. | 1 |
| 20:10, 1 March 2020 | tsarlet 3d plug matrix.png (file) |  |
204 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} 3D-Plug matrix. | 1 |
| 20:10, 1 March 2020 | tsarlet 3d plug ubumps.png (file) |  |
100 KB | David | CEA Leti {{cealeti|TSARLET|l=arch}} 3D-Plug ubumps. | 1 |
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