Semiconductor & Computer Engineering
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| Date | Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 15:20, 21 April 2017 | lincroft clock domains.png (file) |  |
273 KB | David | Intel {{intel|Lincroft|l=core}} clock domains | 1 |
| 16:32, 21 April 2017 | lincroft new egvl mode.png (file) |  |
87 KB | David | Intel {{intel|Bonnell|l=arch}}'s Enhanced Geyserville (eGVL) mode added in Lincroft. | 1 |
| 16:35, 21 April 2017 | lincroft extended c-states.png (file) |  |
114 KB | David | Intel {{intel|Bonnell|l=arch}} extended C-States implemented in {{intel|Lincroft|l=core}} | 1 |
| 16:47, 21 April 2017 | lincroft all on.png (file) |  |
532 KB | David | Intel {{intel|Bonnell|l=arch}}'s {{intel|Lincroft|l=core}}, all power islands on. * All islands off: File:lincroft_all_off.png | 1 |
| 16:47, 21 April 2017 | lincroft all off.png (file) |  |
183 KB | David | Intel {{intel|Bonnell|l=arch}}'s {{intel|Lincroft|l=core}}, all power islands off. * All islands on: File:lincroft_all_on.png | 1 |
| 21:40, 21 April 2017 | kaby lake soc clock domain block diagram.svg (file) |  |
100 KB | David | corrected a typo | 2 |
| 21:40, 21 April 2017 | skylake soc clock domain block diagram.svg (file) |  |
96 KB | David | corrected a typo | 2 |
| 22:24, 21 April 2017 | moorestown platform.pdf (file) |  |
1.53 MB | David | Intel {{intel|Moorestown|l=platform}} | 1 |
| 12:36, 22 April 2017 | oak trail platform.png (file) |  |
114 KB | David | Intel {{intel|Oak Trail|l=platform}} platform | 1 |
| 00:37, 23 April 2017 | lincroft chips.png (file) |  |
542 KB | David | Intel {{intel|Lincroft|l=core}}-based processors | 1 |
| 01:43, 23 April 2017 | atom-z6xx-datasheet.pdf (file) |  |
664 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z6xx Datasheet. | 1 |
| 01:43, 23 April 2017 | atom-z6xx-specification-update.pdf (file) |  |
193 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z6xx Datasheet specs update. | 1 |
| 01:43, 23 April 2017 | atom-z670-datasheet.pdf (file) |  |
580 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z670 Datasheet. | 1 |
| 01:43, 23 April 2017 | atom-z670-specification-update.pdf (file) |  |
140 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z670 Datasheet specs update. | 1 |
| 01:44, 23 April 2017 | atom-z670-z650-sm35-chipset-bios-appl-note.pdf (file) |  |
155 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z670/Z650 with Intel SM35 Express Chipset-Based Platform BIOS Development Vendors and Contacts | 1 |
| 01:44, 23 April 2017 | z670-z650-sm35-express-chipset-paper.pdf (file) |  |
655 KB | David | Intel {{intel|Atom}} ({{intel|Bonnell|l=arch}}, {{intel|Lincroft|l=core}} core) Z670/Z650 chipset paper | 1 |
| 14:01, 24 April 2017 | skylake tdp-form factor range.png (file) |  |
247 KB | David | 2 | |
| 15:48, 24 April 2017 | skylake soc (superset features).png (file) | .png) |
275 KB | David | Intel {{intel|Skylake}} SoC A hypothetical model with all available features ("superset model"). | 1 |
| 03:35, 25 April 2017 | skylake master core configs.svg (file) |  |
8 KB | David | Intel {{intel|Skylake|l=arch}} configurability. | 1 |
| 01:48, 26 April 2017 | 8008 die shot.png (file) |  |
6.14 MB | ChipIt | Intel {{intel|8008}} die shot by Intel. Copyright Intel. | 1 |
| 03:44, 26 April 2017 | 8080 die shot.png (file) |  |
1.98 MB | ChipIt | Intel {{intel|8080}} die shot by Intel. Copyright Intel. | 1 |
| 03:55, 26 April 2017 | pentium pro die shot.png (file) |  |
596 KB | David | Intel {{intel|Pentium Pro}} die shot by Intel. Copyright Intel. | 1 |
| 04:09, 26 April 2017 | pentium die shot.png (file) |  |
1.59 MB | ChipIt | Intel {{intel|Pentium}} ({{intel|P5}}) die shot by Intel. Copyright Intel. | 1 |
| 04:15, 26 April 2017 | 486dx die shot.png (file) |  |
520 KB | ChipIt | Intel {{intel|486DX}} die shot by Intel. Copyright Intel. | 1 |
| 04:16, 26 April 2017 | 386 die shot.png (file) |  |
679 KB | ChipIt | Intel {{intel|386}} die shot by Intel. Copyright Intel. | 1 |
| 04:16, 26 April 2017 | 286 die shot.png (file) |  |
658 KB | ChipIt | Intel {{intel|286}} die shot by Intel. Copyright Intel. | 1 |
| 06:16, 27 April 2017 | intel common arch post ucache.svg (file) |  |
30 KB | ChipIt | dimension adjustment | 2 |
| 19:19, 28 April 2017 | skylake fetch.svg (file) |  |
15 KB | At32Hz | typo | 4 |
| 18:42, 29 April 2017 | skylake 2x core complex die.png (file) |  |
1.51 MB | At32Hz | Intel {{intel|Skylake|l=arch}} 2x core complex from a dual-core die shot by Intel. | 1 |
| 20:40, 29 April 2017 | skylake 4x core complex die.png (file) |  |
5.46 MB | At32Hz | Intel {{intel|Skylake|l=arch}} 4x core complex from a dual-core die shot by Intel. | 1 |
| 19:39, 30 April 2017 | tick-tock (2008).png (file) | .png) |
639 KB | David | 1 | |
| 20:12, 30 April 2017 | skylake core die.png (file) |  |
564 KB | At32Hz | rotated version | 2 |
| 20:14, 30 April 2017 | skylake core die (annotated).png (file) | .png) |
522 KB | At32Hz | removed the shading, it was distracting | 3 |
| 20:41, 30 April 2017 | nehalem die shot.png (file) |  |
8.87 MB | At32Hz | Intel {{intel|Nehalem|l=arch}} die shot by Intel. Copyright Intel. | 1 |
| 21:12, 30 April 2017 | tick-tock (2009).png (file) | .png) |
838 KB | David | 1 | |
| 21:13, 30 April 2017 | tick-tock (2012).png (file) | .png) |
550 KB | David | 1 | |
| 21:50, 30 April 2017 | tick-tock (2014, 2).png (file) | .png) |
294 KB | David | 1 | |
| 21:50, 30 April 2017 | tick-tock (2014).png (file) | .png) |
389 KB | David | 1 | |
| 22:02, 30 April 2017 | 24281603.pdf (file) |  |
498 KB | David | Intel Architecture Optimization Manual ({{intel|P6|l=arch}}) Order Number 242816-003 1997 | 1 |
| 22:11, 30 April 2017 | tick-tock (2013).png (file) | .png) |
179 KB | David | 1 | |
| 22:27, 30 April 2017 | haswell isa extension.pdf (file) |  |
305 KB | David | Intel {{intel|Haswell|l=arch}} new ISA extensions | 1 |
| 22:44, 30 April 2017 | pao.png (file) |  |
570 KB | David | {{intel|PAO}} | 1 |
| 01:58, 1 May 2017 | 01-2 Intel C2 AE Processor Architecture-Core.ppt (file) |  |
1.66 MB | At32Hz | [[Intel]® Processor Micro-architecture – {{intel|Core|l=arch}}® Intel® Software College 2006 | 1 |
| 13:52, 1 May 2017 | core mopf off.png (file) |  |
255 KB | At32Hz | 2 | |
| 13:52, 1 May 2017 | core mopf on.png (file) |  |
251 KB | At32Hz | 2 | |
| 21:07, 1 May 2017 | zen soc.png (file) |  |
1.31 MB | David | AMD {{amd|Zen}} fabrics overview | 1 |
| 02:18, 4 May 2017 | skylake rob.svg (file) |  |
24 KB | At32Hz | Intel {{intel|Skylake|l=arch}} arch ROB | 1 |
| 21:30, 4 May 2017 | skylake soc block diagram.svg (file) |  |
30 KB | At32Hz | another try | 4 |
| 21:31, 4 May 2017 | kaby lake soc block diagram.svg (file) |  |
27 KB | At32Hz | 3 | |
| 21:38, 4 May 2017 | skylake soc block diagram (dual).svg (file) | .svg) |
24 KB | At32Hz | My drawing of {{intel|Skylake|l=arch}} SOC in a block diagram. Dual core SoC. | 1 |
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