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Information for "zhaoxin/kaixian"
Basic information
Display title | KaiXian (ZX/KX) - Zhaoxin |
Default sort key | KaiXian (ZX/KX), Zhaoxin |
Page length (in bytes) | 5,859 |
Page ID | 27789 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
Counted as a content page | Yes |
Number of subpages of this page | 6 (0 redirects; 6 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | ChipIt (talk | contribs) |
Date of page creation | 01:32, 15 January 2018 |
Latest editor | 124.82.18.12 (talk) |
Date of latest edit | 08:23, 27 May 2019 |
Total number of edits | 15 |
Total number of distinct authors | 4 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (19) | Templates used on this page:
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Facts about "KaiXian (ZX/KX) - Zhaoxin"
designer | Zhaoxin + and VIA Technologies + |
first announced | 2016 + |
first launched | 2016 + |
full page name | zhaoxin/kaixian + |
instance of | microprocessor family + |
instruction set architecture | x86 + |
main designer | Zhaoxin + |
manufacturer | TSMC + and HLMC + |
microarchitecture | Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui + |
name | KaiXian + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |