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Information for "xiaomi/surge/s1"
Basic information
Display title | Surge S1 - Xiaomi |
Default sort key | Surge S1, Xiaomi |
Page length (in bytes) | 4,029 |
Page ID | 16997 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 4 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 14:24, 3 March 2017 |
Latest editor | 104.28.90.5 (talk) |
Date of latest edit | 03:42, 7 April 2022 |
Total number of edits | 19 |
Total number of distinct authors | 8 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (14) | Templates used on this page:
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Facts about "Surge S1 - Xiaomi"
base frequency | 1,400 MHz (1.4 GHz, 1,400,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
bus type | AXI + |
core count | 8 + |
core name | Cortex-A53 + |
designer | Xiaomi + and ARM Holdings + |
family | Surge + |
first announced | February 28, 2017 + |
full page name | xiaomi/surge/s1 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | Mali-T860 + |
integrated gpu base frequency | 800 MHz (0.8 GHz, 800,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 4 + |
isa | ARMv8 + |
isa family | ARM + |
ldate | 3000 + |
manufacturer | TSMC + |
market segment | Mobile + |
max memory bandwidth | 13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A53 + |
model number | S1 + |
name | Xiaomi Surge S1 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
supported memory type | LPDDR3-1866 + |
technology | CMOS + |
thread count | 8 + |
used by | Xiaomi Mi 5C, Cubepilot HereLink + |