From WikiChip
Information for "samsung/exynos"
Basic information
Display title | Exynos - Samsung |
Default sort key | Exynos, Samsung |
Page length (in bytes) | 10,821 |
Page ID | 16850 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 4 |
Counted as a content page | Yes |
Number of subpages of this page | 30 (0 redirects; 30 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 15:58, 26 February 2017 |
Latest editor | 95.24.57.52 (talk) |
Date of latest edit | 21:52, 29 March 2025 |
Total number of edits | 26 |
Total number of distinct authors | 10 |
Recent number of edits (within past 90 days) | 1 |
Recent number of distinct authors | 1 |
Page properties
Transcluded templates (28) | Templates used on this page:
|
Facts about "Exynos - Samsung"
designer | Samsung + and ARM Holdings + |
full page name | samsung/exynos + |
instance of | system on a chip family + |
instruction set architecture | ARMv7 + and ARMv8 + |
main designer | Samsung + |
manufacturer | Samsung + |
microarchitecture | Mongoose M1 +, Mongoose M2 +, Mongoose M3 +, Mongoose M4 +, Mongoose M5 +, Cortex-A7 +, Cortex-A8 +, Cortex-A9 +, Cortex-A15 +, Cortex-A53 +, Cortex-A57 +, Cortex-A73 +, Cortex-A75 + and Cortex-A76 + |
name | Samsung Exynos + |
process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 8 nm (0.008 μm, 8.0e-6 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |