Semiconductor & Computer Engineering
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Information for "samsung/exynos"
Basic information
| Display title | Exynos - Samsung |
| Default sort key | Exynos, Samsung |
| Page length (in bytes) | 10,171 |
| Page ID | 16850 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 4 |
| Counted as a content page | Yes |
| Number of subpages of this page | 30 (0 redirects; 30 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 14:58, 26 February 2017 |
| Latest editor | 191.253.12.121 (talk) |
| Date of latest edit | 23:25, 7 November 2023 |
| Total number of edits | 25 |
| Total number of distinct authors | 9 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (26) | Templates used on this page:
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Facts about "Exynos - Samsung"
| designer | Samsung + and ARM Holdings + |
| full page name | samsung/exynos + |
| instance of | system on a chip family + |
| instruction set architecture | ARMv7 + and ARMv8 + |
| main designer | Samsung + |
| manufacturer | Samsung + |
| microarchitecture | Cortex-A7 +, Cortex-A8 +, Cortex-A9 +, Cortex-A15 +, Cortex-A53 +, Cortex-A57 +, Mongoose M1 + and Mongoose M2 + |
| name | Samsung Exynos + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |