Information for "marvell/armada/628"

Basic information

Display title	ARMADA 628 - Marvell
Default sort key	ARMADA 628, Marvell
Page length (in bytes)	5,854
Page ID	18222
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	5
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

Edit	Allow all users (infinite)
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Page creator	David (talk \| contribs)
Date of page creation	15:26, 28 May 2017
Latest editor	92.113.211.174 (talk)
Date of latest edit	16:03, 24 January 2018
Total number of edits	10
Total number of distinct authors	4
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (18)	Templates used on this page: Template:abbr (edit) Template:arch (view source) (protected) Template:arm features (edit) Template:cache size (view source) (protected) Template:chip (view source) (protected) Template:expansions (edit) Template:integrated graphics (edit) Template:istrue (view source) (protected) Template:link-marvell technology (edit) Template:link-vivante (edit) Template:main (view source) (protected) Template:marvell (edit) Template:marvell title (edit) Template:memory controller (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Template:vivante (edit) Module:chip (view source)

base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) + and 624 MHz (0.624 GHz, 624,000 kHz) +
core count	3 +
core name	Sheeva PJ4 +
designer	Marvell +
family	ARMADA 600 +
first announced	September 23, 2010 +
first launched	March 2011 +
full page name	marvell/armada/628 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	GC1000 +
integrated gpu base frequency	500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designer	Vivante +
io voltage	1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance	0.3 V +
isa	ARMv6 + and ARMv5 +
isa family	ARM +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size	96 KiB (98,304 B, 0.0938 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	March 2011 +
main image	+
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory bandwidth	7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels	1 +
microarchitecture	Sheeva PJ4 +
model number	628 +
name	ARMADA 628 +
part number	88AP628 +
platform	ARMADA +
process	55 nm (0.055 μm, 5.5e-5 mm) +
series	600 +
smp max ways	1 +
supported memory type	DDR3-1066 + and DDR2-800 +
thread count	3 +
word size	32 bit (4 octets, 8 nibbles) +