From WikiChip
Information for "intel/xeon gold/5218t"

Basic information

Display titleXeon Gold 5218T - Intel
Default sort keyXeon Gold 5218T, Intel
Page length (in bytes)4,719
Page ID33084
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page7
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation22:40, 3 April 2019
Latest editorDavid (talk | contribs)
Date of latest edit23:22, 28 December 2019
Total number of edits11
Total number of distinct authors1
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (22)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_gold/5218t"
Facts about "Xeon Gold 5218T - Intel"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier21 +
core count16 +
core family6 +
core nameCascade Lake SP +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/5218t +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureCascade Lake +
model number5218T +
nameXeon Gold 5218T +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series5200 +
smp max ways4 +
socketSocket P + and LGA-3647 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count32 +
word size64 bit (8 octets, 16 nibbles) +