Information for "intel/xeon gold/5215l"

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Display title	Xeon Gold 5215L - Intel
Default sort key	Xeon Gold 5215L, Intel
Page length (in bytes)	4,460
Page ID	33088
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	9
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

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Page creator	David (talk \| contribs)
Date of page creation	01:17, 4 April 2019
Latest editor	David (talk \| contribs)
Date of latest edit	22:43, 28 December 2019
Total number of edits	8
Total number of distinct authors	1
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

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Retrieved from "https://en.wikichip.org/wiki/intel/xeon_gold/5215l"

Facts about "Xeon Gold 5215L - Intel"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5215L - Intel#pcie +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	25 +
core count	10 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L0 + and L1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5215l +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ description	16-way set associative +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory	4,718,592 MiB (4,831,838,208 KiB, 4,947,802,324,992 B, 4,608 GiB, 4.5 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	5215L +
name	Xeon Gold 5215L +
package	FCLGA-3647 +
part number	CD8069504214202 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
release price (tray)	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
s-spec	SRFBD +
s-spec (qs)	QRGB +
series	5200 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2666 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	20 +
turbo frequency (1 core)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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