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Information for "intel/xeon e5/e5-2660 v4"
Basic information
Display title | Xeon E5-2660 v4 - Intel |
Default sort key | Xeon E5-2660 v4, Intel |
Page length (in bytes) | 5,017 |
Page ID | 10805 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 8 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 22:49, 2 November 2016 |
Latest editor | ChippyBot (talk | contribs) |
Date of latest edit | 15:27, 13 December 2017 |
Total number of edits | 16 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (17) | Templates used on this page:
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Facts about "Xeon E5-2660 v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2660 v4 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) + |
max pcie lanes | 40 + |