From WikiChip
Information for "intel/xeon e5/e5-2650l v4"

Basic information

Display titleXeon E5-2650L v4 - Intel
Default sort keyXeon E5-2650L v4, Intel
Page length (in bytes)4,993
Page ID10807
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page8
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation23:55, 2 November 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:27, 13 December 2017
Total number of edits15
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (17)

Templates used on this page:

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2650L v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +
max pcie lanes40 +