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Information for "intel/xeon e5"
Basic information
| Display title | Xeon E5 - Intel |
| Default sort key | Xeon E5, Intel |
| Page length (in bytes) | 10,838 |
| Page ID | 10775 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Number of subpages of this page | 55 (0 redirects; 55 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 12:01, 2 November 2016 |
| Latest editor | 95.24.54.109 (talk) |
| Date of latest edit | 13:47, 16 April 2025 |
| Total number of edits | 29 |
| Total number of distinct authors | 8 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (20) | Templates used on this page:
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Facts about "Xeon E5 - Intel"
| designer | Intel + |
| first announced | April 5, 2011 + |
| first launched | April 5, 2011 + |
| full page name | intel/xeon e5 + |
| instance of | microprocessor family + |
| instruction set architecture | x86-64 + |
| main designer | Intel + |
| manufacturer | Intel + |
| microarchitecture | Westmere +, Ivy Bridge +, Haswell + and Broadwell + |
| name | Intel Xeon E5 + |
| package | FCLGA-2011-v3 + |
| process | 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | LGA-2011-v3 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |