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Information for "intel/microarchitectures/rocket lake"
Basic information
| Display title | Rocket Lake - Microarchitectures - Intel |
| Default sort key | Rocket Lake, Intel |
| Page length (in bytes) | 5,382 |
| Page ID | 34783 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 16:33, 4 June 2019 |
| Latest editor | Oleg3280 (talk | contribs) |
| Date of latest edit | 11:55, 20 November 2021 |
| Total number of edits | 26 |
| Total number of distinct authors | 14 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (15) | Templates used on this page:
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Facts about "Rocket Lake - Microarchitectures - Intel"
| codename | Rocket Lake + |
| core count | 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | March 16, 2021 + |
| full page name | intel/microarchitectures/rocket lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Rocket Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |