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Information for "intel/microarchitectures/larrabee"
Basic information
| Display title | Larrabee - Microarchitectures - Intel |
| Default sort key | Larrabee, Intel |
| Page length (in bytes) | 587 |
| Page ID | 29236 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 15:53, 8 April 2018 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 01:49, 31 March 2019 |
| Total number of edits | 5 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
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| Transcluded templates (6) | Templates used on this page:
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Facts about "Larrabee - Microarchitectures - Intel"
| codename | Larrabee + |
| core count | 8 +, 16 +, 24 +, 32 +, 40 + and 48 + |
| designer | Intel + |
| first launched | August 12, 2008 + |
| full page name | intel/microarchitectures/larrabee + |
| instance of | microarchitecture + |
| instruction set architecture | x86 + |
| manufacturer | Intel + |
| microarchitecture type | GPU + |
| name | Larrabee + |
| phase-out | 2010 + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) + and 32 nm (0.032 μm, 3.2e-5 mm) + |