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Information for "intel/microarchitectures/ice lake (server)"
Basic information
Display title | Ice Lake (server) - Microarchitectures - Intel |
Default sort key | Ice Lake (server), Intel |
Page length (in bytes) | 7,768 |
Page ID | 28554 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 3 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | At32Hz (talk | contribs) |
Date of page creation | 18:49, 9 March 2018 |
Latest editor | 84.239.25.18 (talk) |
Date of latest edit | 17:41, 26 March 2024 |
Total number of edits | 29 |
Total number of distinct authors | 15 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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Facts about "Ice Lake (server) - Microarchitectures - Intel"
codename | Ice Lake (server) + |
core count | 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | April 2021 + |
full page name | intel/microarchitectures/ice lake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |