From WikiChip
Information for "intel/microarchitectures/ice lake (server)"

Basic information

Display titleIce Lake (server) - Microarchitectures - Intel
Default sort keyIce Lake (server), Intel
Page length (in bytes)7,768
Page ID28554
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page3
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorAt32Hz (talk | contribs)
Date of page creation18:49, 9 March 2018
Latest editor84.239.25.18 (talk)
Date of latest edit17:41, 26 March 2024
Total number of edits29
Total number of distinct authors15
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (17)

Templates used on this page:

codenameIce Lake (server) +
core count8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 +
designerIntel +
first launchedApril 2021 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (server) +
pipeline stages (max)19 +
pipeline stages (min)14 +