Semiconductor & Computer Engineering
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Information for "intel/cores/cascade lake x"
Basic information
| Display title | Cascade Lake X - Cores - Intel |
| Default sort key | Cascade Lake X, Intel |
| Page length (in bytes) | 820 |
| Page ID | 27156 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 07:41, 5 December 2017 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 12:07, 6 April 2019 |
| Total number of edits | 8 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (14) | Templates used on this page:
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Facts about "Cascade Lake X - Cores - Intel"
| designer | Intel + |
| first announced | April 2019 + |
| first launched | April 2019 + |
| instance of | core + |
| isa | x86-64 + |
| isa family | x86 + |
| manufacturer | Intel + |
| microarchitecture | Cascade Lake + |
| name | Cascade Lake X + |
| package | FCLGA-2066 + |
| platform | Glacier Falls + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | Socket R4 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |