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Information for "intel/cores/cascade lake sp"
Basic information
Display title | Cascade Lake SP - Cores - Intel |
Default sort key | Cascade Lake SP, Intel |
Page length (in bytes) | 9,614 |
Page ID | 29228 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 4 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 21:13, 7 April 2018 |
Latest editor | David (talk | contribs) |
Date of latest edit | 13:48, 27 February 2020 |
Total number of edits | 30 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (20) | Templates used on this page:
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Facts about "Cascade Lake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | December 2018 + |
first launched | March 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | ![]() |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake SP + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |