From WikiChip
Information for "ibm/microarchitectures/power9"
Basic information
| Display title | POWER9 - Microarchitectures - IBM |
| Default sort key | POWER9, IBM |
| Page length (in bytes) | 14,081 |
| Page ID | 16737 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 15:13, 31 January 2017 |
| Latest editor | 134.191.196.183 (talk) |
| Date of latest edit | 10:21, 18 April 2025 |
| Total number of edits | 78 |
| Total number of distinct authors | 9 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (25) | Templates used on this page:
|
Facts about "POWER9 - Microarchitectures - IBM"
| codename | POWER9 + |
| core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
| designer | IBM + |
| first launched | August 2017 + |
| full page name | ibm/microarchitectures/power9 + |
| instance of | microarchitecture + |
| instruction set architecture | Power ISA v3.0B + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | POWER9 + |
| phase-out | 2020 + |
| pipeline stages (max) | 16 + |
| pipeline stages (min) | 12 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |