Semiconductor & Computer Engineering
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Information for "fujitsu/sparc64/sparc64 xii"
Basic information
| Display title | SPARC64 XII - Fujitsu |
| Default sort key | SPARC64 XII, Fujitsu |
| Page length (in bytes) | 3,310 |
| Page ID | 17392 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 3 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 20:32, 12 April 2017 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 14:39, 24 March 2019 |
| Total number of edits | 11 |
| Total number of distinct authors | 4 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (6) | Templates used on this page:
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Facts about "SPARC64 XII - Fujitsu"
| base frequency | 4,250 MHz (4.25 GHz, 4,250,000 kHz) + |
| core count | 12 + |
| designer | Fujitsu + |
| family | SPARC64 + |
| first announced | 2015 + |
| first launched | April 4, 2017 + |
| full page name | fujitsu/sparc64/sparc64 xii + |
| instance of | microprocessor + |
| isa | SPARC V9 + |
| isa family | SPARC + |
| ldate | April 4, 2017 + |
| main image |  + |
| main image caption | SPARC64 XII Chip + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 32 + |
| max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
| microarchitecture | SPARC64 XII + |
| model number | SPARC64 XII + |
| name | SPARC64 XII + |
| process | 20 nm (0.02 μm, 2.0e-5 mm) + |
| smp max ways | 32 + |
| technology | CMOS + |
| thread count | 96 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
