Semiconductor & Computer Engineering
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Information for "cavium/octeon tx/cn8020"
Basic information
| Display title | CN8020 - Cavium |
| Default sort key | CN8020, Cavium |
| Page length (in bytes) | 3,005 |
| Page ID | 32731 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 3 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | 173.76.100.32 (talk) |
| Date of page creation | 19:09, 1 February 2019 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 02:06, 2 February 2019 |
| Total number of edits | 2 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (15) | Templates used on this page:
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Facts about "CN8020 - Cavium"
| base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
| core count | 2 + |
| designer | Cavium + |
| family | OCTEON TX + |
| full page name | cavium/octeon tx/cn8020 + |
| has ecc memory support | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | ArmV8 + |
| isa family | ARM + |
| l1$ size | 208 KiB (212,992 B, 0.203 MiB) + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ size | 144 KiB (147,456 B, 0.141 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | 1900 + |
| market segment | Storage + |
| max cpu count | 1 + |
| microarchitecture | Armv8.1 + |
| name | Octeon TX CN8020 + |
| series | CN80xx + |
| smp max ways | 1 + |
| supported memory type | DDR3/4-2100 + |
| technology | CMOS + |
| thread count | 2 + |
| word size | 64 bit (8 octets, 16 nibbles) + |