Information for "cavium/microarchitectures/vulcan"

Basic information

Display title	Vulcan - Microarchitectures - Cavium
Default sort key	Vulcan, Cavium
Page length (in bytes)	17,035
Page ID	30184
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	4
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

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Page creator	David (talk \| contribs)
Date of page creation	01:28, 27 May 2018
Latest editor	49.37.202.204 (talk)
Date of latest edit	21:11, 4 October 2019
Total number of edits	62
Total number of distinct authors	6
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (25)	Templates used on this page: Template:arch (view source) (protected) Template:arm (edit) Template:broadcom (edit) Template:cavium (edit) Template:cavium title (edit) Template:comp table count (edit) Template:comp table end (edit) Template:comp table header (edit) Template:comp table start (edit) Template:intel (view source) (protected) Template:link-arm (edit) Template:link-broadcom (edit) Template:link-cavium (edit) Template:link-intel (view source) (protected) Template:link-qualcomm (edit) Template:link-raza (edit) Template:microarchitecture (edit) Template:proc table 3 (view source) (protected) Template:qualcomm (edit) Template:raza (edit) Template:tchk (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:comptable (view source) Module:microarchitecture (view source)

codename	Vulcan +
core count	16 +, 20 +, 24 +, 28 +, 30 + and 32 +
designer	Broadcom + and Cavium +
first launched	2018 +
full page name	cavium/microarchitectures/vulcan +
instance of	microarchitecture +
instruction set architecture	ARMv8.1 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Vulcan +
pipeline stages (max)	15 +
pipeline stages (min)	13 +
process	16 nm (0.016 μm, 1.6e-5 mm) +