From WikiChip
Information for "arm holdings/microarchitectures/neoverse v1"
Basic information
Display title | Neoverse V1 - Microarchitectures - ARM |
Default sort key | Neoverse V1, ARM Holdings |
Page length (in bytes) | 7,562 |
Page ID | 36406 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 2 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 00:03, 26 April 2021 |
Latest editor | 95.24.51.108 (talk) |
Date of latest edit | 21:34, 23 March 2025 |
Total number of edits | 4 |
Total number of distinct authors | 3 |
Recent number of edits (within past 90 days) | 1 |
Recent number of distinct authors | 1 |
Page properties
Transcluded templates (17) | Templates used on this page:
|
Facts about "Neoverse V1 - Microarchitectures - ARM"
codename | Neoverse V1 + |
designer | ARM Holdings + |
first launched | April 27, 2021 + |
full page name | arm holdings/microarchitectures/neoverse v1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.4 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse V1 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |