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Display titleNeoverse V1 - Microarchitectures - ARM
Default sort keyNeoverse V1, ARM Holdings
Page length (in bytes)7,562
Page ID36406
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page2
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation00:03, 26 April 2021
Latest editor95.24.51.108 (talk)
Date of latest edit21:34, 23 March 2025
Total number of edits4
Total number of distinct authors3
Recent number of edits (within past 90 days)1
Recent number of distinct authors1

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codenameNeoverse V1 +
designerARM Holdings +
first launchedApril 27, 2021 +
full page namearm holdings/microarchitectures/neoverse v1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.4 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse V1 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +