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Display titleNeoverse N2 - Microarchitectures - ARM
Default sort keyNeoverse N2, ARM Holdings
Page length (in bytes)4,008
Page ID32214
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page1
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation02:16, 14 December 2018
Latest editor95.24.51.108 (talk)
Date of latest edit22:56, 23 March 2025
Total number of edits14
Total number of distinct authors5
Recent number of edits (within past 90 days)2
Recent number of distinct authors1

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codenameNeoverse N2 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedSeptember 22, 2020 +
full page namearm holdings/microarchitectures/neoverse n2 +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N2 +
pipeline stages13 +
process7 nm (0.007 μm, 7.0e-6 mm) +