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Information for "arm holdings/microarchitectures/neoverse n2"
Basic information
Display title | Neoverse N2 - Microarchitectures - ARM |
Default sort key | Neoverse N2, ARM Holdings |
Page length (in bytes) | 4,008 |
Page ID | 32214 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
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Edit history
Page creator | David (talk | contribs) |
Date of page creation | 02:16, 14 December 2018 |
Latest editor | 95.24.51.108 (talk) |
Date of latest edit | 22:56, 23 March 2025 |
Total number of edits | 14 |
Total number of distinct authors | 5 |
Recent number of edits (within past 90 days) | 2 |
Recent number of distinct authors | 1 |
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Facts about "Neoverse N2 - Microarchitectures - ARM"
codename | Neoverse N2 + |
core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
designer | ARM Holdings + |
first launched | September 22, 2020 + |
full page name | arm holdings/microarchitectures/neoverse n2 + |
instance of | microarchitecture + |
instruction set architecture | ARMv9.0-A + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse N2 + |
pipeline stages | 13 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |