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Information for "arm holdings/microarchitectures/neoverse n1"

Basic information

Display titleNeoverse N1 - Microarchitectures - ARM
Default sort keyNeoverse N1, ARM Holdings
Page length (in bytes)8,803
Page ID31122
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page4
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation00:39, 23 August 2018
Latest editor95.24.51.108 (talk)
Date of latest edit17:00, 23 March 2025
Total number of edits35
Total number of distinct authors7
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (15)

Templates used on this page:

codenameCortex-Ares +
designerARM Holdings +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-Ares +
process10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +