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Information for "arm holdings/microarchitectures/neoverse n1"
Basic information
| Display title | Neoverse N1 - Microarchitectures - ARM |
| Default sort key | Neoverse N1, ARM Holdings |
| Page length (in bytes) | 8,803 |
| Page ID | 31122 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 4 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 00:39, 23 August 2018 |
| Latest editor | 95.24.51.108 (talk) |
| Date of latest edit | 17:00, 23 March 2025 |
| Total number of edits | 35 |
| Total number of distinct authors | 7 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (15) | Templates used on this page:
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Facts about "Neoverse N1 - Microarchitectures - ARM"
| codename | Cortex-Ares + |
| designer | ARM Holdings + |
| full page name | arm holdings/microarchitectures/neoverse n1 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-Ares + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |