From WikiChip
Information for "arm holdings/microarchitectures/neoverse n1"

Basic information

Display titleNeoverse N1 - Microarchitectures - ARM
Default sort keyNeoverse N1, ARM Holdings
Page length (in bytes)7,105
Page ID31122
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page5
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation00:39, 23 August 2018
Latest editor83.227.20.170 (talk)
Date of latest edit12:46, 18 February 2023
Total number of edits34
Total number of distinct authors6
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (14)

Templates used on this page:

codenameNeoverse N1 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N1 +
pipeline stages11 +
process7 nm (0.007 μm, 7.0e-6 mm) +