Semiconductor & Computer Engineering
From WikiChip
Information for "arm holdings/microarchitectures/cortex-x1"
Basic information
| Display title | Cortex-X1 (Hera) - Microarchitectures - ARM |
| Default sort key | Cortex-X1 (Hera), ARM Holdings |
| Page length (in bytes) | 11,030 |
| Page ID | 36104 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 08:42, 26 May 2020 |
| Latest editor | 95.24.54.109 (talk) |
| Date of latest edit | 19:43, 15 April 2025 |
| Total number of edits | 7 |
| Total number of distinct authors | 4 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (12) | Templates used on this page:
|
Facts about "Cortex-X1 (Hera) - Microarchitectures - ARM"
| codename | Cortex-X1 (Hera) + |
| core count | 1 +, 2 +, 4 +, 6 + and 8 + |
| designer | ARM Holdings + |
| first launched | May 26, 2020 + |
| full page name | arm holdings/microarchitectures/cortex-x1 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-X1 (Hera) + |
| pipeline stages | 13 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |