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Information for "arm holdings/microarchitectures/cortex-a78"
Basic information
| Display title | Cortex-A78 - Microarchitectures - ARM |
| Default sort key | Cortex-A78, ARM Holdings |
| Page length (in bytes) | 21,305 |
| Page ID | 31128 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 00:53, 23 August 2018 |
| Latest editor | 71.192.103.47 (talk) |
| Date of latest edit | 08:25, 31 March 2022 |
| Total number of edits | 9 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
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| Transcluded templates (18) | Templates used on this page:
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Facts about "Cortex-A78 - Microarchitectures - ARM"
| codename | Cortex-A78 + |
| core count | 1 +, 2 +, 4 +, 6 + and 8 + |
| designer | ARM Holdings + |
| first launched | May 26, 2020 + |
| full page name | arm holdings/microarchitectures/cortex-a78 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A78 + |
| pipeline stages | 13 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |