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Information for "arm holdings/microarchitectures/cortex-a53"
Basic information
| Display title | Cortex-A53 - Microarchitectures - ARM |
| Default sort key | Cortex-A53, ARM Holdings |
| Page length (in bytes) | 6,056 |
| Page ID | 11887 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 34 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 15:15, 3 December 2016 |
| Latest editor | 14.228.191.122 (talk) |
| Date of latest edit | 09:34, 30 October 2025 |
| Total number of edits | 44 |
| Total number of distinct authors | 12 |
| Recent number of edits (within past 90 days) | 1 |
| Recent number of distinct authors | 1 |
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| Transcluded templates (18) | Templates used on this page:
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Facts about "Cortex-A53 - Microarchitectures - ARM"
| codename | Cortex-A53 + |
| core count | 1 +, 2 +, 3 + and 4 + |
| designer | ARM Holdings + |
| first launched | October 30, 2012 + |
| full page name | arm holdings/microarchitectures/cortex-a53 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC +, Samsung + and GlobalFoundries + |
| microarchitecture type | CPU + |
| name | Cortex-A53 + |
| pipeline stages | 8 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |