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Information for "amd/cores/colfax"
Basic information
Display title | Colfax - Cores - AMD |
Default sort key | Colfax, AMD |
Page length (in bytes) | 2,767 |
Page ID | 31024 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 2 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 11:45, 11 August 2018 |
Latest editor | 209.222.170.17 (talk) |
Date of latest edit | 15:57, 22 December 2021 |
Total number of edits | 9 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (21) | Templates used on this page:
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Facts about "Colfax - Cores - AMD"
designer | AMD + |
first announced | August 6, 2018 + |
first launched | August 13, 2018 + |
instance of | core + |
isa | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen+ + |
name | Colfax + |
package | TR4 + and FCLGA-4094 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
socket | TR4 +, SP3r2 + and sTR4 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |