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Information for "amd/cores/chagall"
Basic information
Display title | Chagall - Cores - AMD |
Default sort key | Chagall, AMD |
Page length (in bytes) | 8,149 |
Page ID | 35713 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 13:59, 1 January 2020 |
Latest editor | QuietRub (talk | contribs) |
Date of latest edit | 13:26, 17 March 2023 |
Total number of edits | 5 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
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Facts about "Chagall - Cores - AMD"
designer | AMD + |
first launched | March 8, 2022 + |
instance of | core + |
isa | x86-64 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture | Zen 3 + |
name | Chagall + |
package | sWRX8 + and FCLGA-4094 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
socket | sWRX8 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |