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Information for "amd/cores/castle peak"
Basic information
Display title | Castle Peak - Cores - AMD |
Default sort key | Castle Peak, AMD |
Page length (in bytes) | 7,073 |
Page ID | 31025 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 11:47, 11 August 2018 |
Latest editor | 95.24.50.104 (talk) |
Date of latest edit | 17:52, 14 December 2024 |
Total number of edits | 25 |
Total number of distinct authors | 9 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (22) | Templates used on this page:
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Facts about "Castle Peak - Cores - AMD"
back image | File:20 + |
chipset | TRX40 +, WRX80 + and 1 + |
designer | AMD + and 1 + |
fate | 1 + |
first announced | November 7, 2019 + |
first launched | November 25, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | File:20 + |
main image caption | 1 + |
manufacturer | TSMC +, GlobalFoundries + and 1 + |
microarchitecture | Zen 2 + and 1 + |
name | Castle Peak + |
package | sTRX4 +, FCLGA-4094 + and sWRX8 + |
platform | 1 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
socket | sTRX4 + and sWRX8 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |