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Information for "amd/cores/castle peak"

Basic information

Display titleCastle Peak - Cores - AMD
Default sort keyCastle Peak, AMD
Page length (in bytes)7,073
Page ID31025
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page1
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation10:47, 11 August 2018
Latest editorQuietRub (talk | contribs)
Date of latest edit13:16, 17 March 2023
Total number of edits23
Total number of distinct authors7
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (22)

Templates used on this page:

chipsetTRX40 + and WRX80 +
designerAMD +
first announcedNovember 7, 2019 +
first launchedNovember 25, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 2 +
nameCastle Peak +
packagesTRX4 +, FCLGA-4094 + and sWRX8 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +
socketsTRX4 + and sWRX8 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +