Revision history of "renesas/r-car/h3 (sip)"

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(cur | prev) 01:38, 23 July 2017‎ BCD (talk | contribs)‎ . . (470 bytes) (+470)‎ . . (Created page with "{{renesas title|R-Car H3 (SiP}} {{mpu}} '''R-Car H3''' is a {{arch|64}} nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. T...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car H3 (SiP) - Renesas#package +
core count	9 +
core name	Cortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage	0.8 V (8 dV, 80 cV, 800 mV) +
designer	Renesas + and ARM Holdings +
die area	111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length	12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width	8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
family	R-Car +
first announced	December 2, 2015 +
first launched	March 2018 +
full page name	renesas/r-car/h3 (sip) +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR GX6650 +
integrated gpu designer	Imagination Technologies +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv8 +
isa family	ARM +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ size	288 KiB (294,912 B, 0.281 MiB) +
l1i$ size	352 KiB (360,448 B, 0.344 MiB) +
l2$ size	2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldate	March 2018 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory bandwidth	47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A53 +, Cortex-A57 + and Cortex-R7 +
model number	H3 (SiP) +
name	R-Car H3 (SiP) +
package	FCBGA-1255 +
part number	R8J77950 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
series	3rd Gen +
smp max ways	1 +
supported memory type	LPDDR4-3200 +
technology	CMOS +
thread count	9 +
word size	64 bit (8 octets, 16 nibbles) +

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