Revision history of "nvidia/microarchitectures/denver"

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(cur | prev) 08:10, 11 February 2020‎ 193.137.92.138 (talk)‎ . . (5,788 bytes) (0)‎ . . (→‎Products) (undo)
(cur | prev) 21:39, 28 February 2019‎ 222.72.155.214 (talk)‎ . . (5,788 bytes) (-25)‎ . . (undo)
(cur | prev) 22:11, 29 August 2018‎ David (talk | contribs)‎ . . (5,813 bytes) (+67)‎ . . (undo)
(cur | prev) 18:30, 18 June 2018‎ A5b (talk | contribs)‎ . . (5,746 bytes) (+5)‎ . . (parker trm 17.4.3.17 crc32 sha1 aes sha2 advanced simd? and https://github.com/ssvb/tinymembench/wiki/Nexus-9-(Tegra-TK1-T132---Denver)) (undo)
(cur | prev) 18:16, 18 June 2018‎ A5b (talk | contribs)‎ . . (5,741 bytes) (+139)‎ . . (→‎Architecture: some bits from parker trm) (undo)
(cur | prev) 18:11, 18 June 2018‎ A5b (talk | contribs)‎ . . (5,602 bytes) (+267)‎ . . (some denver 2 armv8 features from parker trm) (undo)
(cur | prev) 18:09, 18 June 2018‎ A5b (talk | contribs)‎ . . (5,335 bytes) (+963)‎ . . (add cache+tlb from Parker TRM info; denver 2 may be described there too.) (undo)
(cur | prev) 12:58, 16 June 2018‎ Inject (talk | contribs)‎ . . (4,372 bytes) (-920)‎ . . (undo)
(cur | prev) 12:57, 16 June 2018‎ Inject (talk | contribs)‎ . . (5,292 bytes) (+5)‎ . . (title) (undo)
(cur | prev) 12:42, 16 June 2018‎ A5b (talk | contribs)‎ m . . (5,287 bytes) (+11)‎ . . (Tegra X2 is another name of parker) (undo)
(cur | prev) 12:31, 16 June 2018‎ A5b (talk | contribs)‎ . . (5,276 bytes) (+36)‎ . . (→‎Architecture: update pipeline stage actions with linley descriptions piazza.com/class_profile/get_resource/hzbgxhrhoe322v/i2ctm26s481e1) (undo)
(cur | prev) 12:28, 16 June 2018‎ A5b (talk | contribs)‎ . . (5,240 bytes) (+231)‎ . . (→‎Architecture: stealing pipeline table from section 12 of ibm/microarchitectures/power9) (undo)
(cur | prev) 12:23, 16 June 2018‎ A5b (talk | contribs)‎ m . . (5,009 bytes) (0)‎ . . (A5b moved page nvidia/denver to nvidia/microarchitectures/denver: Move to microarchitectures subsection) (undo)
(cur | prev) 12:12, 16 June 2018‎ A5b (talk | contribs)‎ . . (5,009 bytes) (+130)‎ . . (→‎Products: Denver 2 is used in Nvidia's Terga Parker (2016, 16 nm TSMC). Parker SoC also uses 4 Cortex-A57 cores.) (undo)
(cur | prev) 12:09, 16 June 2018‎ A5b (talk | contribs)‎ . . (4,879 bytes) (+47)‎ . . (https://www.anandtech.com/tag/project-denver) (undo)
(cur | prev) 12:07, 16 June 2018‎ A5b (talk | contribs)‎ . . (4,832 bytes) (-11)‎ . . (split for nvidia/denver2 - nvidia parker - https://www.anandtech.com/show/10596/hot-chips-2016-nvidia-discloses-tegra-parker-details) (undo)
(cur | prev) 12:05, 16 June 2018‎ A5b (talk | contribs)‎ . . (4,843 bytes) (+1,248)‎ . . (→‎Architecture: based on HC26.11.234-Denver-Darrell.Boggs-NVIDIA-rev4.pdf) (undo)
(cur | prev) 11:55, 16 June 2018‎ A5b (talk | contribs)‎ . . (3,595 bytes) (-16)‎ . . (| type = Superscalar - hc26) (undo)
(cur | prev) 11:54, 16 June 2018‎ A5b (talk | contribs)‎ . . (3,611 bytes) (+238)‎ . . (→‎References: rev4.pdf IEEE HotChips 26 (HC26), 2014] - Darrell Boggs "Nvidia's Denver Processor") (undo)
(cur | prev) 11:51, 16 June 2018‎ A5b (talk | contribs)‎ . . (3,373 bytes) (+101)‎ . . (Denver is used in Tegra K1-64) (undo)
(cur | prev) 11:48, 16 June 2018‎ A5b (talk | contribs)‎ . . (3,272 bytes) (+3,272)‎ . . (Start based on mpr 14 article Nvidia_Denverreprint.pdf)

codename	Denver +
core count	2 +
designer	Nvidia +
first launched	2014 +
full page name	nvidia/microarchitectures/denver +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	4-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Denver +
process	28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +

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