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Revision history of "nervana/nnp/nnp-t 1300"
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Facts about "NNP-T 1300 - Intel Nervana"
back image | + |
base frequency | 950 MHz (0.95 GHz, 950,000 kHz) + |
core count | 22 + |
designer | Intel + |
die area | 680 mm² (1.054 in², 6.8 cm², 680,000,000 µm²) + |
family | NNP + |
first announced | November 12, 2019 + |
first launched | November 12, 2019 + |
full page name | nervana/nnp/nnp-t 1300 + |
has ecc memory support | true + |
instance of | microprocessor + |
ldate | November 12, 2019 + |
main image | + |
main image caption | NPU with 4 HBM2 stacks + |
manufacturer | TSMC + |
market segment | Server + |
max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) + |
max memory bandwidth | 1,144.409 GiB/s (1,171,875 MiB/s, 1,228.8 GB/s, 1,228,800 MB/s, 1.118 TiB/s, 1.229 TB/s) + |
max memory channels | 32 + |
microarchitecture | Spring Crest + |
model number | NNP-T 1300 + |
name | NNP-T 1300 + |
package | FCBGA-3325 + |
peak flops (half-precision) | 93,390,000,000,000 FLOPS (93,390,000,000 KFLOPS, 93,390,000 MFLOPS, 93,390 GFLOPS, 93.39 TFLOPS, 0.0934 PFLOPS, 9.339e-5 EFLOPS, 9.339e-8 ZFLOPS) + |
power dissipation | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | NNP-T + |
smp interconnect | InterChip Link + |
smp interconnect links | 16 + |
smp interconnect rate | 28 GT/s + |
supported memory type | HBM2-2400 + |
tdp | 300 W (300,000 mW, 0.402 hp, 0.3 kW) + |
technology | CMOS + |
transistor count | 27,000,000,000 + |