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Facts about "Xeon D-1612 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-1612 - Intel#pcie + |
| back image | |
| base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
| bus type | DMI 2.0 + |
| clock multiplier | 15 + |
| core count | 4 + |
| core family | 6 + |
| core model | 6 + |
| core name | Hewitt Lake + |
| core stepping | A1 + |
| designer | Intel + |
| die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
| family | Xeon D + |
| first announced | April 2, 2019 + |
| first launched | April 2, 2019 + |
| full page name | intel/xeon d/d-1612 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Secure Key Technology + and OS Guard + |
| has intel enhanced speedstep technology | true + |
| has intel secure key technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| ldate | April 2, 2019 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 365.15 K (92 °C, 197.6 °F, 657.27 °R) + |
| max cpu count | 1 + |
| max junction temperature | 378.15 K (105 °C, 221 °F, 680.67 °R) + |
| max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
| max memory bandwidth | 31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| max sata ports | 6 + |
| max usb ports | 4 + |
| microarchitecture | Broadwell + |
| model number | D-1612 + |
| name | Xeon D-1612 + |
| package | FCBGA-1667 + |
| part number | GG8068204236701 + |
| platform | Grangeville + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| s-spec | SRG06 + |
| series | D-1600 + |
| smp max ways | 1 + |
| supported memory type | DDR4-2133 + |
| tdp | 22 W (22,000 mW, 0.0295 hp, 0.022 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| transistor count | 3,200,000,000 + |
| turbo frequency (1 core) | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |