Revision history of "amd/epyc/7232p"

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(cur | prev) 01:29, 19 August 2022‎ 198.27.191.231 (talk)‎ . . (5,186 bytes) (-1)‎ . . (I have one of these, it appears to be two chiplets, with half the cache disabled. Setting the BIOS to have a NUMA domain per LLC results in four numa domains. Also, 'lscpu' reports 4 L3 'instances') (undo)
(cur | prev) 18:51, 9 January 2021‎ QuietRub (talk | contribs)‎ . . (5,187 bytes) (0)‎ . . (Fixed part number.) (undo)
(cur | prev) 17:11, 4 January 2021‎ QuietRub (talk | contribs)‎ . . (5,187 bytes) (+1,906)‎ . . (Fixed clock multiplier, added missing data, added die count and memory bandwidth note.) (undo)
(cur | prev) 11:38, 6 January 2020‎ David (talk | contribs)‎ m . . (3,281 bytes) (+6)‎ . . (Reverted edits by 79.55.11.15 (talk) to last revision by David) (undo)
(cur | prev) 06:11, 5 January 2020‎ 79.55.11.15 (talk)‎ . . (3,275 bytes) (-6)‎ . . (The low-end SKUs don't support full 8-channel memory bandwidth. See https://www.amd.com/en/products/cpu/amd-epyc-7232p https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf) (undo)
(cur | prev) 18:18, 7 August 2019‎ David (talk | contribs)‎ . . (3,281 bytes) (0)‎ . . (undo)
(cur | prev) 18:17, 7 August 2019‎ David (talk | contribs)‎ . . (3,281 bytes) (+20)‎ . . (undo)
(cur | prev) 18:17, 7 August 2019‎ David (talk | contribs)‎ . . (3,261 bytes) (0)‎ . . (undo)
(cur | prev) 18:16, 7 August 2019‎ David (talk | contribs)‎ m . . (3,261 bytes) (0)‎ . . (David moved page amd/epyc/7252p to amd/epyc/7232p without leaving a redirect) (undo)
(cur | prev) 16:59, 6 August 2019‎ David (talk | contribs)‎ . . (3,261 bytes) (-216)‎ . . (undo)
(cur | prev) 16:57, 6 August 2019‎ David (talk | contribs)‎ . . (3,477 bytes) (+482)‎ . . (undo)
(cur | prev) 16:44, 6 August 2019‎ David (talk | contribs)‎ . . (2,995 bytes) (+1,079)‎ . . (undo)
(cur | prev) 15:53, 6 August 2019‎ David (talk | contribs)‎ . . (1,916 bytes) (+287)‎ . . (undo)
(cur | prev) 15:24, 6 August 2019‎ David (talk | contribs)‎ . . (1,629 bytes) (+387)‎ . . (undo)
(cur | prev) 15:14, 6 August 2019‎ David (talk | contribs)‎ . . (1,242 bytes) (+597)‎ . . (undo)
(cur | prev) 13:15, 6 August 2019‎ David (talk | contribs)‎ . . (645 bytes) (-1)‎ . . (undo)
(cur | prev) 13:12, 6 August 2019‎ David (talk | contribs)‎ . . (646 bytes) (+2)‎ . . (undo)
(cur | prev) 13:11, 6 August 2019‎ David (talk | contribs)‎ . . (644 bytes) (+6)‎ . . (undo)
(cur | prev) 13:09, 6 August 2019‎ David (talk | contribs)‎ . . (638 bytes) (+5)‎ . . (undo)
(cur | prev) 12:56, 6 August 2019‎ David (talk | contribs)‎ . . (633 bytes) (+600)‎ . . (undo)
(cur | prev) 11:53, 6 August 2019‎ David (talk | contribs)‎ . . (33 bytes) (+33)‎ . . (Created page with "{{amd title|EPYC 7252P}} {{chip}}")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7232P - AMD#pcie +
base frequency	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
clock multiplier	31 +
core count	8 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	2 +
family	EPYC +
first announced	August 7, 2019 +
first launched	August 7, 2019 +
full page name	amd/epyc/7232p +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	August 7, 2019 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	1 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7232P +
name	EPYC 7232P +
package	SP3 + and FCLGA-4094 +
part number	100-000000081 + and 100-100000081WOF +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 450.00 (€ 405.00, £ 364.50, ¥ 46,498.50) +
series	7002 +
smp max ways	1 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-3200 +
tdp	120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technology	CMOS +
thread count	16 +
turbo frequency	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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