Revision history of "intel/microarchitectures/alder lake"

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(cur | prev) 02:19, 17 November 2021‎ 199.30.186.83 (talk)‎ . . (6,327 bytes) (+161)‎ . . (undo)
(cur | prev) 02:02, 17 November 2021‎ 199.30.186.83 (talk)‎ . . (6,166 bytes) (+13)‎ . . (undo)
(cur | prev) 12:16, 7 November 2021‎ 99.151.34.247 (talk)‎ . . (6,153 bytes) (+84)‎ . . (Added links to core architecture names.) (undo)
(cur | prev) 08:39, 7 November 2021‎ 31.9.174.28 (talk)‎ . . (6,069 bytes) (0)‎ . . (→‎Brands) (undo)
(cur | prev) 19:07, 5 November 2021‎ David (talk | contribs)‎ . . (6,069 bytes) (+2,642)‎ . . (undo)
(cur | prev) 23:35, 4 November 2021‎ 116.254.117.34 (talk)‎ . . (3,427 bytes) (0)‎ . . (fix wrong e core count) (undo)
(cur | prev) 12:49, 4 November 2021‎ David (talk | contribs)‎ . . (3,427 bytes) (+40)‎ . . (→‎ADL-S (8P+8E)) (undo)
(cur | prev) 14:36, 3 November 2021‎ David (talk | contribs)‎ . . (3,387 bytes) (+771)‎ . . (undo)
(cur | prev) 14:27, 3 November 2021‎ David (talk | contribs)‎ . . (2,616 bytes) (+425)‎ . . (undo)
(cur | prev) 14:13, 3 November 2021‎ David (talk | contribs)‎ . . (2,191 bytes) (+18)‎ . . (→‎Die) (undo)
(cur | prev) 07:47, 3 November 2021‎ David (talk | contribs)‎ . . (2,173 bytes) (+5)‎ . . (→‎Die) (undo)
(cur | prev) 07:44, 3 November 2021‎ David (talk | contribs)‎ . . (2,168 bytes) (+693)‎ . . (undo)
(cur | prev) 20:03, 28 October 2021‎ 67.87.35.128 (talk)‎ . . (1,475 bytes) (-3)‎ . . (→‎History) (undo)
(cur | prev) 14:30, 11 August 2021‎ 223.235.190.20 (talk)‎ . . (1,478 bytes) (+2)‎ . . (punctuation corrections) (undo)
(cur | prev) 14:27, 11 August 2021‎ 223.235.190.20 (talk)‎ . . (1,476 bytes) (+195)‎ . . (Event Updates) (undo)
(cur | prev) 14:18, 11 August 2021‎ 223.235.190.20 (talk)‎ . . (1,281 bytes) (-21)‎ . . (updating node names) (undo)
(cur | prev) 14:17, 11 August 2021‎ 223.235.190.20 (talk)‎ . . (1,302 bytes) (+13)‎ . . (Updating Node Conventions) (undo)
(cur | prev) 09:16, 24 May 2021‎ 86.127.244.44 (talk)‎ . . (1,289 bytes) (+10)‎ . . (undo)
(cur | prev) 09:18, 14 May 2021‎ David (talk | contribs)‎ . . (1,279 bytes) (-158)‎ . . (undo)
(cur | prev) 05:12, 10 April 2021‎ 60.50.71.219 (talk)‎ . . (1,437 bytes) (-6)‎ . . (undo)
(cur | prev) 14:03, 26 March 2021‎ 192.55.54.53 (talk)‎ . . (1,443 bytes) (+10)‎ . . (ALderlake can support any memory config) (undo)
(cur | prev) 09:50, 26 March 2021‎ 110.159.98.99 (talk)‎ . . (1,433 bytes) (0)‎ . . (https://www.intel.com/content/www/us/en/search.html?ws=text#q=%22Raptor%20Lake%22&t=All "Provides customers an overview of high-level compatibility guidance between Alder Lake S and Raptor Lake S") (undo)
(cur | prev) 09:34, 7 March 2021‎ 81.242.26.227 (talk)‎ . . (1,433 bytes) (+10)‎ . . (undo)
(cur | prev) 09:34, 7 March 2021‎ 81.242.26.227 (talk)‎ . . (1,423 bytes) (-41)‎ . . (removed unnecessary mention from "ThE LeAkEr" that actually leaked nothing) (undo)
(cur | prev) 08:16, 22 February 2021‎ 145.133.190.164 (talk)‎ . . (1,464 bytes) (+88)‎ . . (More details in key changes from tiger lake) (undo)
(cur | prev) 11:05, 3 February 2021‎ 145.133.190.164 (talk)‎ . . (1,376 bytes) (+287)‎ . . (→‎History) (undo)
(cur | prev) 06:43, 3 February 2021‎ 145.133.190.164 (talk)‎ . . (1,089 bytes) (+83)‎ . . (undo)
(cur | prev) 06:10, 3 February 2021‎ 145.133.190.164 (talk)‎ . . (1,006 bytes) (+173)‎ . . (Process Technology updated) (undo)
(cur | prev) 06:07, 3 February 2021‎ 145.133.190.164 (talk)‎ . . (833 bytes) (+53)‎ . . (Improvements of Alder Lake) (undo)
(cur | prev) 07:11, 12 January 2021‎ 111.107.210.162 (talk)‎ . . (780 bytes) (+84)‎ . . (undo)
(cur | prev) 03:31, 1 October 2020‎ 110.159.129.107 (talk)‎ . . (696 bytes) (+48)‎ . . (undo)
(cur | prev) 11:53, 7 September 2020‎ 98.194.48.86 (talk)‎ . . (648 bytes) (-48)‎ . . (undo)
(cur | prev) 11:55, 15 August 2020‎ 210.187.238.108 (talk)‎ . . (696 bytes) (+80)‎ . . (Alder Lake is successor to Tiger Lake, it's high performance, not low power like Lakefield) (undo)
(cur | prev) 23:35, 14 August 2020‎ Qwetional (talk | contribs)‎ . . (616 bytes) (-80)‎ . . (undo)
(cur | prev) 04:11, 14 August 2020‎ 210.187.238.108 (talk)‎ . . (696 bytes) (+12)‎ . . (https://newsroom.intel.com/wp-content/uploads/sites/11/2020/08/Intel-Architecture-Day-2020-Presentation-Slides.pdf) (undo)
(cur | prev) 05:16, 21 July 2020‎ 60.52.45.117 (talk)‎ . . (684 bytes) (+2)‎ . . (undo)
(cur | prev) 05:09, 21 July 2020‎ 60.52.45.117 (talk)‎ . . (682 bytes) (+170)‎ . . (https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2242174.html →‎Hybrid Core/Atom Processors: #define INTEL_FAM6_ALDERLAKE 0x97) (undo)
(cur | prev) 17:53, 3 February 2019‎ David (talk | contribs)‎ m . . (512 bytes) (0)‎ . . (Reverted edits by 122.57.53.251 (talk) to last revision by David) (undo)
(cur | prev) 15:49, 3 February 2019‎ 122.57.53.251 (talk)‎ . . (512 bytes) (0)‎ . . (undo)
(cur | prev) 07:10, 18 May 2018‎ David (talk | contribs)‎ m . . (512 bytes) (+2)‎ . . (undo)
(cur | prev) 07:50, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (510 bytes) (-1)‎ . . (undo)
(cur | prev) 01:02, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (511 bytes) (+12)‎ . . (undo)
(cur | prev) 01:01, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (499 bytes) (+25)‎ . . (undo)
(cur | prev) 00:48, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (474 bytes) (+1)‎ . . (undo)
(cur | prev) 00:48, 6 April 2018‎ ChipIt (talk | contribs)‎ . . (473 bytes) (+168)‎ . . (undo)
(cur | prev) 22:50, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (305 bytes) (+78)‎ . . (undo)
(cur | prev) 22:45, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (227 bytes) (+33)‎ . . (undo)
(cur | prev) 22:42, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (194 bytes) (+20)‎ . . (undo)
(cur | prev) 22:42, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (174 bytes) (+121)‎ . . (undo)
(cur | prev) 22:41, 5 April 2018‎ ChipIt (talk | contribs)‎ . . (53 bytes) (+53)‎ . . (Created page with "{{intel title|Alder Lake|arch}} {{microarchitecture}}")

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codename	Alder Lake +
core count	16 +, 14 +, 10 + and 6 +
designer	Intel +
first launched	2021 +
full page name	intel/microarchitectures/alder lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Alder Lake +
process	10 nm (0.01 μm, 1.0e-5 mm) +
processing element count	8P/8E +, 6P/8E +, 2P/8E +, 6P/0E +, 32 EU iGPU + and 96 EU iGPU +

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