Editing umich/microarchitectures/celerity

{{title|Celerity - Microarchitectures}}
{{microarchitecture
|atype=CPU
|name=Celerity
|designer=University of Michigan
|designer 2=University of Washington
|designer 3=Cornell University
|designer 4=University of California
|manufacturer=TSMC
|process=16 nm
|isa=RISC-V
|extension=Integer
|extension 2=Multiply
}}
'''Celerity''' is a custom [[RISC-V]]-based [[neural processor]] microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.

== Etymology ==
Celerity means 'swiftness of movement' which is the intended purpose of the architecture.

== Process technology ==
Celerity is fabricated on [[TSMC]] [[16 nm process]].

== Overview ==
Celerity is a university-based research chip designed for the [[acceleration]] of [[neural processor|artificial intelligence]]. The design and implementation of the chip was said to have taken just nine months through the use of agile development and leveraging existing [[open-source]] code. The design is intended to allow enough flexibility as AI workloads continue to evolve. Designed for [[TSMC]] [[16 nm process]], the chip integrates three separate tiers of architectures, each is progressively more specialized, less flexible, but more power-efficient. The first tier, the general-purpose tier, integrates five powerful [[RISC-V]] {{ucberkeley|Rocket}} [[cores]] capable of running an operating system and managing the rest of the SoC. The second tier, the massively parallel tier, integrates a [[massively parallel processor array|massive array]] of 496 parallel highly-efficient, but simple, [[RISC-V]] {{\\|Vanilla-5}} cores. The last tier is the specialization tier which integrates a specialized custom [[binarized neural network|BNN]] [[accelerator]].

== Compute tiers ==
{{empty section}}
=== General-purpose  tier ===
{{empty section}}
=== Massively parallel tier ===
{{empty section}}
=== Specialization tier ===
{{empty section}}

== Die ==
{{empty section}}

== Bibliography ==
* {{bib|vlsi|2019}}
* {{bib|hc|29}}
codename	Celerity +
designer	University of Michigan +, University of Washington +, Cornell University + and University of California +
full page name	umich/microarchitectures/celerity +
instance of	microarchitecture +
instruction set architecture	RISC-V +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Celerity +
process	16 nm (0.016 μm, 1.6e-5 mm) +