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This chip was first presented at the ''2016 IEEE Symposium on VLSI Circuits'' on June 17, 2016. It has also been published in the ''IEEE Journal of Solid-State Circuits (JSSC), IEEE HotChips, IEEE Micro,'' and ''ACM/IEEE DAC''. | This chip was first presented at the ''2016 IEEE Symposium on VLSI Circuits'' on June 17, 2016. It has also been published in the ''IEEE Journal of Solid-State Circuits (JSSC), IEEE HotChips, IEEE Micro,'' and ''ACM/IEEE DAC''. | ||
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+ | Contrary to many online reports, the KiloCore is the second not the first microprocessor to achieve 1,000 or more cores. The {{pezy|PEZY-SC}} reached the milestone first but was not published in a venue with publicly-available proceedings. | ||
== Architecture == | == Architecture == | ||
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* 768 KB SRAM on-die | * 768 KB SRAM on-die | ||
** 12 shared SRAM memory modules, 64 KB each | ** 12 shared SRAM memory modules, 64 KB each | ||
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== Designers == | == Designers == |
Facts about "KiloCore - UC Davis"
base frequency | 1,780 MHz (1.78 GHz, 1,780,000 kHz) + |
core count | 1,000 + |
designer | UC Davis +, Brent Bohnenstiehl +, Aaron Stillmaker + and Bevan Baas + |
die area | 64 mm² (0.0992 in², 0.64 cm², 64,000,000 µm²) + |
first announced | June 17, 2016 + |
full page name | uc davis/kilocore + |
instance of | microprocessor + |
ldate | June 17, 2016 + |
main image | + |
main image caption | KiloCore on a daughterboard + |
manufacturer | IBM + |
name | KiloCore + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
technology | CMOS + |
transistor count | 621,000,000 + |
word size | 16 bit (2 octets, 4 nibbles) + |