From WikiChip
Editing samsung/microarchitectures/m5
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 2: | Line 2: | ||
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=Mongoose 5 |
|designer=Samsung | |designer=Samsung | ||
|manufacturer=Samsung | |manufacturer=Samsung | ||
|introduction=2020 | |introduction=2020 | ||
− | |process= | + | |process=8 nm |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|predecessor=M4 | |predecessor=M4 | ||
|predecessor link=samsung/microarchitectures/m4 | |predecessor link=samsung/microarchitectures/m4 | ||
+ | |successor=cancelled | ||
}} | }} | ||
− | '''Exynos | + | '''Exynos Mongoose 5''' ('''M5''') is the successor to the {{\\|Mongoose 4}}, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. |
+ | |||
+ | |||
+ | {{future information}} | ||
== Process Technology == | == Process Technology == | ||
− | The M5 is fabricated on Samsung's [[7 nm process]] (7LPP). | + | The M5 is planned to be fabricated on Samsung's [[7 nm process]] (7LPP). |
== Compiler support == | == Compiler support == | ||
Line 49: | Line 32: | ||
=== Key changes from {{\\|M4}} === | === Key changes from {{\\|M4}} === | ||
− | + | {{empty section}} | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Block Diagram === | === Block Diagram === | ||
==== Individual Core ==== | ==== Individual Core ==== | ||
− | [[File:mongoose 5 block diagram.svg| | + | [[File:mongoose 5 block diagram.svg|900px]] |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− |
Facts about "Exynos M5 - Microarchitectures - Samsung"
codename | Lion M5 + |
core count | 2 + |
designer | Samsung + |
first launched | 2020 + |
full page name | samsung/microarchitectures/m5 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Lion M5 + |
pipeline stages | 16 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |