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|first launched=October, 2018 | |first launched=October, 2018 | ||
|family=Exynos | |family=Exynos | ||
− | |series=Exynos | + | |series=Exynos 7 |
|frequency=2,300 MHz | |frequency=2,300 MHz | ||
− | |frequency 2=1, | + | |frequency 2=1,600 MHz |
|isa=ARMv8 | |isa=ARMv8 | ||
|isa family=ARM | |isa family=ARM | ||
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|thread count=8 | |thread count=8 | ||
|max cpus=1 | |max cpus=1 | ||
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− | |||
}} | }} | ||
'''Exynos 9610''' is a {{arch|64}} [[ARM]] mid-range microprocessor designed by [[Samsung]] set to launch in late [[2018]]. Manufactured on Samsung's [[10 nm process]], the 9610 features eight cores consisting of four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.3 GHz and four {{armh|Cortex-A53|l=arch}} [[little cores]] operating at up to 1.6 GHz. This processor incorporates a {{armh|Mali-G72}} MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as [[802.11ac]], [[Bluetooth]] 5.0, and a 24 [[megapixel|MP]] [[image signal processor|ISP]]. | '''Exynos 9610''' is a {{arch|64}} [[ARM]] mid-range microprocessor designed by [[Samsung]] set to launch in late [[2018]]. Manufactured on Samsung's [[10 nm process]], the 9610 features eight cores consisting of four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.3 GHz and four {{armh|Cortex-A53|l=arch}} [[little cores]] operating at up to 1.6 GHz. This processor incorporates a {{armh|Mali-G72}} MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as [[802.11ac]], [[Bluetooth]] 5.0, and a 24 [[megapixel|MP]] [[image signal processor|ISP]]. | ||
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+ | {{unknown features}} | ||
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+ | |||
+ | == Cache == | ||
+ | {{main|arm_holdings/microarchitectures/cortex-a73#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A73 § Cache||l2=Cortex-A55 § Cache}} | ||
+ | |||
+ | For the {{armh|Cortex-A73|l=arch}} core cluster: | ||
+ | {{cache size}} | ||
+ | |||
+ | For the {{armh|Cortex-A55|l=arch}} cluster: | ||
+ | |||
+ | {{cache size}} | ||
== Memory controller == | == Memory controller == | ||
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|channels=4 | |channels=4 | ||
|width=16 bit | |width=16 bit | ||
− | |frequency= | + | |frequency=1800 MHz |
|bandwidth schan=2.98 GiB/s | |bandwidth schan=2.98 GiB/s | ||
|bandwidth dchan=5.96 GiB/s | |bandwidth dchan=5.96 GiB/s | ||
|bandwidth qchan=11.92 GiB/s | |bandwidth qchan=11.92 GiB/s | ||
}} | }} | ||
+ | |||
== Graphics == | == Graphics == | ||
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== ISP == | == ISP == | ||
− | * | + | * 24MP Rear |
− | * | + | * 24MP Front |
* 16MP+16MP Dual | * 16MP+16MP Dual | ||
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== Utilizing devices == | == Utilizing devices == | ||
− | + | <!-- | |
− | * [[used by:: | + | * [[used by::XXXXXXXXX]] |
− | + | --> | |
{{expand list}} | {{expand list}} |
Facts about "Exynos 9610 - Samsung"