From WikiChip
Editing renesas/r-car/h2
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Facts about "R-Car H2 - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car H2 - Renesas#package + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) + |
core count | 9 + |
core name | Cortex A15 +, Cortex A7 + and SH-4A + |
core voltage | 1 V (10 dV, 100 cV, 1,000 mV) + |
designer | Renesas + and ARM Holdings + |
family | R-Car + |
first announced | March 25, 2013 + |
first launched | June 2014 + |
full page name | renesas/r-car/h2 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | PowerVR G6400 + |
integrated gpu base frequency | 550 MHz (0.55 GHz, 550,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 1 + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) + |
isa | ARMv7 + and SuperH + |
isa family | ARM + and SuperH + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1i$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
ldate | June 2014 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex A15 +, Cortex A7 + and SH-4A + |
model number | H2 + |
name | R-Car H2 + |
package | FCBGA-831 + |
part number | R8A7790 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | 2nd Gen + |
smp max ways | 1 + |
supported memory type | DDR3-1600 + |
technology | CMOS + |
thread count | 9 + |
word size | 32 bit (4 octets, 8 nibbles) + |