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{{pezy title|PEZY-1}}
 
{{pezy title|PEZY-1}}
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{{chip
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{{mpu
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|name=PEZY-1
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| name               = PEZY-1
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|image=pezy 1.jpg
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| no image           = Yes
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|designer=PEZY
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| image              =
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|manufacturer=TSMC
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| image size          =
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|model number=PEZY-1
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| caption            =  
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|market=Industrial
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| designer           = PEZY
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|first announced=2011
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| manufacturer       = TSMC
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|first launched=2012
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| model number       = PEZY-1
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|frequency=533.33 MHz
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| part number        =
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|process=40 nm
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| market             = Industrial
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|technology=CMOS
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| first announced     = 2011
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|die area=335 mm²
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| first launched     = 2012
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|die length=16.8 mm
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| last order          =
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|die width=21 mm
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| last shipment      =
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|core count=512
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|power=35 W
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| family              =
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|tjunc min=<!-- °C -->
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| series              =
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|electrical=Yes
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| locked              =
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|packaging=Yes
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| frequency           = 533.33 MHz
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|package 0=fcBGA-1517
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| bus type            =
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|package 0 type=fcBGA
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| bus speed          = 66.66 MHz
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|package 0 pins=1517
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| bus rate            =
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|package 0 pitch=1 mm
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| clock multiplier    = 8
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|package 0 width=40 mm
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|package 0 length=40 mm
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| microarch          =
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|package 0 height=3.01 mm
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| platform            =
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|socket 0=BGA-1517
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| chipset            =
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|socket 0 type=BGA
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| core name          =
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}}
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| core family        =
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'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].  
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| core model          =
 +
| core stepping      =
 +
| process             = 40 nm
 +
| transistors        =
 +
| technology         = CMOS
 +
| die area           = 335 mm²
 +
| die width          = 21 mm
 +
| die length         = 16.8 mm
 +
| word size          =  
 +
| core count         = 512
 +
| thread count        =
 +
| max cpus            =
 +
| max memory          =
 +
| max memory addr    =
 +
 
 +
| electrical          = Yes
 +
| power               = 35 W
 +
| v core              =
 +
| v core tolerance    =
 +
| v io                =
 +
| v io tolerance      =
 +
| sdp                =
 +
| tdp                =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up            =
 +
| ctdp up frequency  =
 +
| temp min            =
 +
| temp max            =
 +
| tjunc min           = <!-- °C -->
 +
| tjunc max          =
 +
| tcase min          =
 +
| tcase max          =
 +
| tstorage min        =
 +
| tstorage max        =  
 +
 
 +
| packaging           = Yes
 +
| package 0           = fcBGA-1517
 +
| package 0 type     = fcBGA
 +
| package 0 pins     = 1517
 +
| package 0 pitch     = 1 mm
 +
| package 0 width     = 40 mm
 +
| package 0 length   = 40 mm
 +
| package 0 height   = 3.01 mm
 +
| socket 0           = BGA-1517
 +
| socket 0 type       = BGA}}
 +
'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peach performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].
  
−
The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the {{pezy|PEZY-SC}}, with twice as many cores and formed the basis for the {{pezy|PEZY-SCx}} family.
+
The PEZY-1 is used for image processing devices and various medical instruments.
  
 
== Cache ==
 
== Cache ==
−
PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 16 KiB (2x) and no L2$.
+
PEZY-1's cache is seperate from the {{armh|ARM926}}'s cache which has an L1$ of 16KB (2x) and no L2$.
−
{{cache size
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{{cache info
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|l1 cache=128 KiB
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|l1 cache=128 KB
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|l1i cache=64 KiB
+
|l1 break=
−
|l1i break=1x64 KiB
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|l1 desc=
−
|l1d cache=64 KiB
+
|l1 extra=
−
|l1d break=1x64 KiB
+
|l2 cache=1 MB
−
|l2 cache=1 MiB
+
|l2 break=
−
|l2 break=1x1 MiB
+
|l2 desc=
 +
|l2 extra=
 +
|l3 cache=0 KB
 +
|l3 desc=No L3$
 
}}
 
}}
  
 
== Memory controller ==
 
== Memory controller ==
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{{memory controller
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{{integrated memory controller
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|type=DDR3-1333
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| type               = DDR3-1333
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|ecc=Yes
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| controllers       = 1
−
|controllers=4
+
| channels           = 4
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|channels=4
+
| ecc support        = <!-- ?? -->
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|width=64 bit
+
| bandwidth schan    = 10,666 MB/s
−
|max bandwidth=39.74 GiB/s
+
| bandwidth dchan    = 21,333 MB/s
−
|bandwidth schan=9.93 GiB/s
+
| bandwidth qchan    = 42,666 MB/s
−
|bandwidth dchan=19.86 GiB/s
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| max memory        = 64 GB
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|bandwidth qchan=39.74 GiB/
 
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{mpu expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
−
| pcie lanes        = 24
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| pcie lanes        = 4
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| pcie config        = 6x4
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| pcie config        =  
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| uart              = Yes
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| pcie config 1      =
−
| gp io              = Yes
+
| pcie config 2      =
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb ports          =
 +
| sata revision      =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              =  
 +
| gp io              =  
 
}}
 
}}
  
 
== PEZY-1 Quad PCI Board ==
 
== PEZY-1 Quad PCI Board ==
 
[[File:pezy 1 quad pci board.jpg|200px|right]]
 
[[File:pezy 1 quad pci board.jpg|200px|right]]
−
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
+
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
  
 
== Documents ==
 
== Documents ==
 
* [[:File:pezy 1 board.pdf|PEZY-1 Board]]
 
* [[:File:pezy 1 board.pdf|PEZY-1 Board]]
 
* [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]]
 
* [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]]

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Facts about "PEZY-1 - PEZY"
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PEZY-1 - PEZY#io +
base frequency533.33 MHz (0.533 GHz, 533,330 kHz) +
core count512 +
designerPEZY +
die area335 mm² (0.519 in², 3.35 cm², 335,000,000 µm²) +
die length16.8 mm (1.68 cm, 0.661 in, 16,800 µm) +
die width21 mm (2.1 cm, 0.827 in, 21,000 µm) +
first announced2011 +
first launched2012 +
full page namepezy/pezy-1 +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2012 +
main imageFile:pezy 1.jpg +
manufacturerTSMC +
market segmentIndustrial +
max memory bandwidth39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) +
max memory channels4 +
max pcie lanes24 +
model numberPEZY-1 +
namePEZY-1 +
power dissipation35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
process40 nm (0.04 μm, 4.0e-5 mm) +
supported memory typeDDR3-1333 +
technologyCMOS +