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|introduction=November 17, 2016 | |introduction=November 17, 2016 | ||
|process=28 nm | |process=28 nm | ||
− | |successor= | + | |successor=Springs Crest |
|successor link=nervana/microarchitectures/spring crest | |successor link=nervana/microarchitectures/spring crest | ||
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== Architecture == | == Architecture == | ||
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* Tensor-based architecture | * Tensor-based architecture | ||
** Nervana Engine | ** Nervana Engine | ||
* [[Flexpoint]] number format | * [[Flexpoint]] number format | ||
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* HBM2 memory | * HBM2 memory | ||
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{{expand list}} | {{expand list}} | ||
=== Block Diagram === | === Block Diagram === | ||
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{{empty section}} | {{empty section}} | ||
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* 32 GiB on-package [[HBM2]] | * 32 GiB on-package [[HBM2]] | ||
** 1 TiB/s | ** 1 TiB/s | ||
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Facts about "Lake Crest - Microarchitectures - Intel Nervana"
codename | Lake Crest + |
designer | Nervana + |
first launched | November 17, 2016 + |
full page name | nervana/microarchitectures/lake crest + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | Lake Crest + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |