Editing mediatek/mt65xx/mt6595

{{mediatek title|MT6595}}
{{chip
|name=MT6595
|no image=Yes
|designer=MediaTek
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=MT6595
|part number=MT6595
|market=Mobile
|first announced=Februray 11, 2014
|first launched=Februray 11, 2014
|family=MT65xx
|frequency=2,500 MHz
|frequency 2=1,700 MHz
|isa=ARMv7
|isa family=ARM
|microarch=Cortex-A17
|microarch 2=Cortex-A7
|core name=Cortex-A17
|core name 2=Cortex-A7
|process=28 nm
|technology=CMOS
|die area=89 mm²
|word size=64 bit
|core count=8
|thread count=8
|max cpus=1
}}
'''MT6595''' is a mid-range octa-core [[ARM]] [[LTE]] SoC designed by [[MediaTek]] and introduced in early 2014. This chip, which is fabricated on TSMC's [[28 nm process]], features four [[big core|big]] {{armh|Cortex-A17|l=arch}} cores operating at up to 2.5 GHz and four [[little core|little]] {{armh|Cortex-A7|l=arch}} cores operating at up to 1.7 GHz. The MT6595 incorporates an PowerVR G6200 GPU operating at up to 600 MHz and supports up to dual-channel LPDDR3-1866 memory.

== Cache ==
{{main|arm_holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A7 § Cache}}

{{armh|Cortex-A7|l=arch}} Cluster:

{{cache size
|l2 cache=512 KiB
|l2 break=1x512 KiB
}}

{{armh|Cortex-A17|l=arch}} Cluster:

{{cache size
|l2 cache=2 MiB
|l2 break=1x2 MiB
}}

== Memory controller ==
{{memory controller
|type=LPDDR3-1866
|ecc=No
|controllers=1
|channels=2
}}

== Graphics ==
{{integrated graphics
| gpu                 = PowerVR G6200
| device id           = 
| designer            = Imagination Technologies
| execution units     =
| max displays        = 
| max memory          = 
| frequency           = 600 MHz

| output dsi          = Yes

| max res dsi         = 2560x1600

| direct3d ver        = 10.0
| opencl ver          = 1.2
| opengl ver          = 3.2
| opengl es ver       = 3.1
| vulkan ver          = 1.0
}}

* Encoding H.265
* Playback H.264,  H.265 / HEVC,  VP-9

== Camera ==
* Image signal processor
** 20 Mpixel

== Connectivity ==
* UE Cat-4
* EDGE,  FDD / TDD LTE,  HSPA +,  TD-SCDMA
* Bluetooth
* Wi-Fi
** a/b/g/n/ac

== Location ==
* GNSS
** GPS, Glonass, Beidou, Galileo

== Utilizing devices ==
* [[used by::Gionee P7 Max]]
* [[used by::InFocus M530]]
* [[used by::Zopo ZP999]]
* [[used by::Meizu MX4]]

{{expand list}}

== Die ==
* TSMC [[28 nm process]]
* 89 mm² die size
* Quad-core {{armh|Cortex-A7|l=arch}}
** ~0.48 mm² per core
* Quad-core {{armh|Cortex-A17|l=arch}} + 2 MiB L2
** ~1.93 mm² per core
** ~3.93 mm² for 2 MiB L2

(small quad-core is unlabeled below the big core cluster)
:[[File:mt6595 die shot.png|600px]]

== Bibliography ==
* Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) + and 1,700 MHz (1.7 GHz, 1,700,000 kHz) +
core count	8 +
core name	Cortex-A17 + and Cortex-A7 +
designer	MediaTek + and ARM Holdings +
die area	89 mm² (0.138 in², 0.89 cm², 89,000,000 µm²) +
family	MT65xx +
first announced	November 2014 +
first launched	November 2014 +
full page name	mediatek/mt65xx/mt6595 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR G6200 +
integrated gpu base frequency	600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu designer	Imagination Technologies +
isa	ARMv7 +
isa family	ARM +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + and 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	November 2014 +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory channels	2 +
microarchitecture	Cortex-A17 + and Cortex-A7 +
model number	MT6595 +
name	MT6595 +
part number	MT6595 +
process	28 nm (0.028 μm, 2.8e-5 mm) +
smp max ways	1 +
supported memory type	LPDDR3-1866 +
technology	CMOS +
thread count	8 +
used by	Gionee P7 Max +, InFocus M530 +, Zopo ZP999 + and Meizu MX4 +
word size	64 bit (8 octets, 16 nibbles) +