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{{intel title|Xeon Silver 4114}} | {{intel title|Xeon Silver 4114}} | ||
− | {{ | + | {{mpu |
|name=Xeon Silver 4114 | |name=Xeon Silver 4114 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
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|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
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|core count=10 | |core count=10 | ||
|thread count=20 | |thread count=20 | ||
+ | |max cpus=2 | ||
|max memory=768 GiB | |max memory=768 GiB | ||
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|tdp=85 W | |tdp=85 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=78 °C | |tcase max=78 °C | ||
− | + | |package module 1={{packages/intel/fclga-3647}} | |
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}} | }} | ||
− | '''Xeon Silver 4114''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114, which is based on the server configuration of the {{intel | + | '''Xeon Silver 4114''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=640 KiB | |l1 cache=640 KiB | ||
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|freq_avx512_10=1,400 MHz | |freq_avx512_10=1,400 MHz | ||
}} | }} | ||
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Facts about "Xeon Silver 4114 - Intel"