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{{intel title|Xeon Gold 6134}} | {{intel title|Xeon Gold 6134}} | ||
− | {{ | + | {{mpu |
+ | |future=Yes | ||
|name=Xeon Gold 6134 | |name=Xeon Gold 6134 | ||
− | |image= | + | |no image=Yes |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6134 | |model number=6134 | ||
− | |part number | + | |part number=CD8067303330302 |
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|s-spec=SR3AR | |s-spec=SR3AR | ||
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|market=Server | |market=Server | ||
|first announced=April 25, 2017 | |first announced=April 25, 2017 | ||
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|family=Xeon Gold | |family=Xeon Gold | ||
|series=6100 | |series=6100 | ||
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|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=32 | |clock multiplier=32 | ||
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|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
+ | |die area=<!-- XX mm² --> | ||
|word size=64 bit | |word size=64 bit | ||
− | |core count= | + | |core count=18 |
− | |thread count= | + | |thread count=36 |
− | + | |max cpus=2 | |
− | |max cpus= | + | |v core tolerance=<!-- OR ... --> |
− | | | + | |v io 2=<!-- OR ... --> |
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|tdp=130 W | |tdp=130 W | ||
− | | | + | |temp min=<!-- use TJ/TC whenever possible instead --> |
− | + | |tjunc min=<!-- .. °C --> | |
− | | | + | |package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> |
− | + | |turbo frequency=Yes | |
− | |package | + | |package module 1={{packages/intel/fclga-3647}} |
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}} | }} | ||
− | '''Xeon Gold 6134''' is a {{arch|64}} [[ | + | '''Xeon Gold 6134''' is a {{arch|64}} [[x86]] high-performance server [[octadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6134 operates at 3.2 GHz with a TDP of 130 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz for a single core. |
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+ | {{unknown features}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
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{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=1.125 MiB |
− | |l1i cache= | + | |l1i cache=576 KiB |
− | |l1i break= | + | |l1i break=18x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |l1d cache= | + | |l1d cache=576 KiB |
− | |l1d break= | + | |l1d break=18x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache= | + | |l2 cache=18 MiB |
− | |l2 break= | + | |l2 break=18x1 MiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
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|type=DDR4-2666 | |type=DDR4-2666 | ||
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem= |
− | |controllers= | + | |controllers=1 |
|channels=6 | |channels=6 | ||
|max bandwidth=119.21 GiB/s | |max bandwidth=119.21 GiB/s | ||
− | |bandwidth schan=19. | + | |bandwidth schan=19.89 GiB/s |
− | |bandwidth dchan=39. | + | |bandwidth dchan=39.72 GiB/s |
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
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}} | }} | ||
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|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | | | + | |avx512=Yes |
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|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
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|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=No |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=No |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
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|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
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|ipt=No | |ipt=No | ||
|tsx=Yes | |tsx=Yes | ||
− | |txt= | + | |txt=No |
|ht=Yes | |ht=Yes | ||
|vpro=Yes | |vpro=Yes | ||
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|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=Yes |
|sgx=No | |sgx=No | ||
|securekey=No | |securekey=No | ||
− | |osguard= | + | |osguard=Yes |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
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|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
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|rvi=No | |rvi=No | ||
|smt=No | |smt=No | ||
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|xfr=No | |xfr=No | ||
}} | }} | ||
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Facts about "Xeon Gold 6134 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6134 - Intel +, Xeon Gold 6134 - Intel + and Xeon Gold 6134 - Intel#io + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 32 + |
core count | 8 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/6134 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 352.15 K (79 °C, 174.2 °F, 633.87 °R) + |
max cpu count | 4 + |
max dts temperature | 100 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 6134 + |
name | Xeon Gold 6134 + |
package | FCLGA-3647 + |
part number | CD8067303330302 + and BX806736134 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,214.00 (€ 1,992.60, £ 1,793.34, ¥ 228,772.62) + |
s-spec | SR3AR + |
s-spec (qs) | QMRL + |
series | 6100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 130 W (130,000 mW, 0.174 hp, 0.13 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |